Embedded chip packages and methods for manufacturing an embedded chip package
AssigneeInfineon Technologies AG
InventorsGottfried Beer, Walter Hartner
Life of this patent
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Abstract
A method for manufacturing an embedded chip package is provided. The method may include: forming electrically conductive lines over a substrate; placing the substrate next to a chip arrangement comprising a chip, the chip comprising one or more contact pads, wherein one or more of the electrically conductive lines are arranged proximate to a side wall of the chip; and forming one or more electrical interconnects over the chip arrangement to electrically connect at least one electrically conductive line to at least one contact pad.
Claims24
A method for manufacturing an embedded chip package, the method comprising forming electrically conductive lines over a substrate;
- placing the substrate next to a chip arrangement comprising a chip, the chip comprising one or more contact pads, wherein one or more of the electrically conductive lines are arranged proximate to a side wall of the chip;
- and
- forming one or more electrical interconnects over the chip arrangement to electrically connect at least one electrically conductive line to at least one contact pad.
A method for manufacturing an embedded chip package, the method comprising
- forming one or more successive layers of electrically conductive lines over a first substrate side, each layer comprising a plurality of electrically conductive lines, wherein each layer is covered by electrically insulating material at least partially surrounding the electrically conductive lines;
- placing a surface of the substrate next to a chip arrangement comprising a chip, the chip comprising one or more contact pads, wherein the electrically conductive lines are arranged proximate to a side wall of the chip;
- and
- forming at least one electrical interconnect over the chip arrangement to electrically connect at least one electrically conductive line to at least one contact pad.
An embedded chip package comprising:
- a chip arrangement comprising a chip comprising one or more contact pads;
- an electrically conductive line arrangement comprising one or more successive layers of electrically conductive lines formed over a first substrate side, each layer comprising a plurality of electrically conductive lines;
- wherein a surface of the substrate is embedded with the chip arrangement;
- wherein the electrically conductive lines are arranged proximate to a side wall of the chip;
- and
- at least one electrical interconnect disposed over the chip arrangement, the at least one electrical interconnect electrically connecting at least one electrically conductive line to at least one contact pad.
An embedded chip package comprising:
- a chip arrangement comprising a chip;
- an electrically conductive line arrangement comprising a layer of electrically conductive lines;
- wherein the electrically conductive line arrangement is arranged next to a side of the chip arrangement, wherein the electrically conductive line arrangement is vertically aligned to a side wall of the chip;
- and
- at least one electrical interconnect disposed over the chip arrangement and the electrically conductive line arrangement, the at least one electrical interconnect electrically connecting at least one electrically conductive line to the chip.
Dependencies are inferred from the claim text.