Bump-on-trace interconnection structure for flip-chip packages
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYu-Jen TSENG, Yen-Liang LIN, Tin-Hao KUO, Chen-Shien CHEN, Mirng-Ji LII
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Abstract
A bump-on-trace interconnection structure utilizing a lower volume solder joint for joining a conductive metal pillar and a metal line trace includes a conductive metal pillar having a bonding surface having a width WP and a metal line trace, provided on a package substrate, having a top surface with a width WT, where WP is greater than WT. The solder joint is bonded to the bonding surface by wetting across the width WP and bonded predominantly only to the top surface of the metal line trace by wetting predominantly only to the top surface across the width WT.
Claims20
(canceled)
A packaging assembly comprising:
- an IC chip comprising a conductive metal pillar having a sidewall and a bonding surface that has a width WP;
- a package substrate having a metal line trace provided thereon, the metal line trace having a top surface that has a width WT and two sidewalls extending downward from the top surface and having a height HT, wherein WP is greater that WT;
- and
- a solder joint joining the conductive metal pillar and the metal line trace, wherein the solder joint is bonded to the bonding surface of the conductive metal pillar substantially across the width WP of the bonding surface and bonded predominantly to the top surface of the metal line trace and the solder joint is bonded to at least one of the two sidewalls of the metal line trace along a minimum wetting portion of the sidewalls of the metal line trace, wherein the minimum wetting portion of the sidewalls extend downward from the top surface no more than ⅕ of the height HT of the sidewalls of the metal line trace.
(canceled)
A bump-on-trace interconnection structure comprising:
- a conductive metal pillar having a sidewall and a bonding surface that has a width WP;
- a metal line trace provided on a package substrate, the metal line trace having a top surface that has a width WT and two sidewalls extending downward from the top surface and having a height HT, wherein WP is greater than WT;
- and
- a solder joint joining the conductive metal pillar and the metal line trace, wherein the solder joint is bonded to the bonding surface of the conductive metal pillar substantially across the width WP of the bonding surface and bonded predominantly to the top surface of the metal line trace and the solder joint is bonded to at least one of the two sidewalls of the metal line trace along a minimum wetting portion of the sidewalls, wherein the minimum wetting portion of the sidewalls extend downward from the top surface no more than ⅕ of the height HT of the sidewalls of the metal line trace.
A packaging assembly comprising:
- an IC chip comprising a conductive metal pillar having a sidewall and a bonding surface that has a width WP;
- a package substrate having a metal line trace provided thereon, the metal line trace having a top surface that has a width WT and two sidewalls extending downward from the top surface and having a height HT, wherein WP is greater that WT;
- and
- a solder joint joining the conductive metal pillar and the metal line trace, wherein the solder joint is bonded to the bonding surface of the conductive metal pillar substantially across the width WP of the bonding surface and bonded predominantly to the top surface of the metal line trace and the solder joint is bonded to at least one of the two sidewalls of the metal line trace along a minimum wetting portion of the sidewalls of the metal line trace, wherein the minimum wetting portion of the sidewalls extend downward from the top surface no more than ⅕ of the height HT of the sidewalls of the metal line trace,
- wherein the sidewall of the conductive metal pillar is covered with a layer of a metal oxide,
- wherein the conductive metal pillar is made of copper or a copper-based alloy and the metal oxide is copper oxide.
Dependencies are inferred from the claim text.