Routing layer for mitigating stress in a semiconductor die
AssigneeATI Technologies ULC
InventorsRoden Topacio, Gabriel Wong
Life of this patent
Estimating the term…
Abstract
A routing layer for a semiconductor die is disclosed. The routing layer includes pads for attaching solder bumps; bond-pads bonded to bump-pads of a die having an integrated circuit, and traces interconnecting bond-pads to pads. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces at least partially surrounding some pads so as to absorb stress from solder bumps attached to the pads. Parts of the traces that surround pads protect parts of the underlying dielectric material proximate the solder bumps, from the stress.
Claims16
A semiconductor die comprising:
- i) an integrated circuit formed on one surface of a piece of semiconductor wafer;
- ii) a plurality of input-output (I/O) pads interconnected to said integrated circuit;
- iii) a routing layer comprising:
- a dielectric layer formed on said one surface;
- and a plurality of conductive traces formed on said dielectric layer, each of said conductive traces extending from one of said I/O pads;
- iv) a plurality of under-bump metallizations (UBMs), each comprising a top surface for attaching a respective one of a plurality of solder bumps;
- and a bottom contact surface smaller than said top surface, in electrical contact with a respective one of said plurality connective traces;
- wherein at least some of said conductive traces pass beneath one of said UBMs without electrically contacting said one of said UBMs, to mechanically reinforce said routing layer proximate said one of said UBMs.
A semiconductor die, comprising:
- i) at least one integrated circuit formed on one surface, and a plurality of input-output (I/O) pads connected to said at least one integrated circuit;
- ii) a routing layer comprising a dielectric layer formed on said surface of said die, and a plurality of conductive traces formed on said dielectric layer, each of said conductive traces extending from one of said I/O pads;
- and
- iii) a plurality of solder bumps formed on corresponding under-bump metallizations (UBMs), each in electrical contact with a respective one of said conductive traces, for electrically interconnecting said integrated circuit to a substrate;
- wherein at least one of said UBMs has at least some of said conductive traces passing through a circular area circumscribing said one of said UBMs without electrically contacting said one of said UBMs, to mechanically reinforce said routing layer proximate said contained bump-pad.
A routing layer for a semiconductor die, said routing layer comprising:
- i) a plurality of I/O interconnecting structures for attaching solder bumps using a plurality of under-bump metallizations (UBMs);
- ii) a plurality of conductive traces interconnecting corresponding ones of said I/O interconnecting structures and a plurality of input-output (I/O) pads of an integrated circuit formed on a die;
- at least one of said conductive traces passing beneath one of said UBMs without contacting that one of said UBMs, to mechanically reinforce said routing layer proximate said corresponding one of said UBMs.
Dependencies are inferred from the claim text.