Semiconductor device and method for manufacturing semiconductor device
AssigneeFuji Electric Co., Ltd.
InventorsShuhei TATEMICHI, Takeyoshi NISHIMURA, Yasushi NIIMURA, Masanori INOUE
Life of this patent
Estimating the term…
Loading patent…
AssigneeFuji Electric Co., Ltd.
InventorsShuhei TATEMICHI, Takeyoshi NISHIMURA, Yasushi NIIMURA, Masanori INOUE
Estimating the term…
A MOS semiconductor device has a MOS structure, including a p− region that surrounds an n+-type source region and has a net doping concentration lower than a concentration of a p-type impurity in a surface of a p-type well region, and a gate electrode that is provided on top of the surface of the p-type well region sandwiched between the n+-type source region and a surface layer of an n− layer, with a gate insulator disposed between the p-type well region and the gate electrode. This configuration can make the gate insulator thicker without increasing a gate threshold voltage, and help improve the reliability of the gate insulator and reduce the gate capacitance.
A semiconductor device having an insulated gate structure,
A method for manufacturing a semiconductor device,
A method for manufacturing a semiconductor device,
A semiconductor device, comprising:
Dependencies are inferred from the claim text.