Structure and method for forming a low gate resistance high-k metal gate transistor device

A method for forming a low gate resistance high-k metal gate transistor device, comprising:

• forming a set of gate stacks and a trench over a substrate, the set of gate stacks and the trench having a n-type work function (nWF) layer along a top surface;
• applying a gas plasma over the n-type work function (nWF) layer of the set of gate stacks and the trench;
• forming a metal layer over the gas plasma treated layer;
• and
• applying a temperature in a range of about 400° C. to about 480° C. to the device to cause a reflow of the metal layer.

A low gate resistance high-k metal gate transistor device, comprising:

• a set of gate stacks in a trench formed over a substrate;
• the set of gate stacks having an initial n-type work function (nWF) layer on top surface of the device;
• a nitridized nWF layer formed on the top surface of the nWF layer through a nitrogen containing gas plasma treatment;
• and
• an aluminum (Al) containing layer formed over the gas nitridized nWF layer to fill the trench during device reflow.