Power Converter Package Including Top-Drain Configured Power FET

A semiconductor package comprising:

• a power converter switching stage including a control vertical FET in a control active die and a sync vertical FET in a sync active die;
• said control vertical FET having a source situated on a source side of said control active die and a drain and a gate situated on a drain side of said control active die;
• said sync vertical FET having a source and a gate situated on a source side of said sync active die and a drain situated on a drain side of said sync active die;
• a conductive carrier being attached to said source side of said control active die and to said drain side of said sync active die;
• said conductive carrier providing a switch node of said power converter switching stage.

A method for fabricating a semiconductor package, said method comprising:

• providing a top-drain vertical FET in a first active die, a source of said top-drain vertical FET situated on a source side of said first active die and a drain and a gate of said top-drain vertical FET situated on a drain side of said first active die;
• providing a bottom-drain vertical FET in a second active die, a source and a gate of said bottom-drain vertical FET situated on a source side of said second active die and a drain of said bottom-drain vertical FET situated on a drain side of said second active die;
• attaching a conductive carrier to said source side of said first active die and to said drain side of said second active die;
• utilizing said conductive carrier to couple said source of said top-drain vertical FET to said drain of said bottom-drain vertical FET.