Layout Schemes for Cascade MOS Transistors

A device comprising:

• a semiconductor substrate comprising an active region strip;
• a first, a second, a third, and a fourth gate electrode parallel to each other, crossing the active region strip, and forming a first, a second, a third, and a fourth Metal-Oxide-Semiconductor (MOS) device that are of a same conductivity type with the active region strip;
• a first common source/drain region between the first and the second gate electrodes, wherein the first common source/drain region is shared by the first and the second MOS devices;
• a second common source/drain region between the second and the third gate electrodes, wherein the second common source/drain region is shared by the second and the third MOS devices;
• a third common source/drain region between the third and the fourth gate electrodes, wherein the third common source/drain region is shared by the third and the fourth MOS devices;
• a first electrical connection interconnecting the first gate electrode and the fourth gate electrode;
• a second electrical connection interconnecting the second gate electrode and the third gate electrode;
• and
• a first contact plug over and connected to the second common source/drain region, wherein no contact plug is over and connected to the first common source/drain region.

A device comprising:

• a plurality of fingers identical to each other, each comprising:
• a first Metal-Oxide-Semiconductor (MOS) device comprising:
• a first gate, wherein the first gates of the first MOS devices in the plurality of fingers are interconnected;
• a first source/drain region, wherein the first source/drain regions of the first MOS devices in the plurality of fingers are interconnected;
• and
• a second source/drain region;
• and
• a second MOS device cascaded with the first MOS device, wherein the first and the second MOS devices have a same conductivity type, and wherein the second MOS device comprises:
• a second gate, wherein the second gates of the second MOS devices in the plurality of fingers are interconnected;
• a third source/drain region forming a common source/drain region with the second source/drain region, wherein the common source/drain regions in the plurality of fingers are disconnected from each other;
• and
• a fourth source/drain region, wherein the fourth source/drain regions of the second MOS devices in the plurality of fingers are interconnected.