Thin film transistor, array substrate, and manufacturing method thereof
AssigneeBoe Technology Group Co., Ltd.
InventorYinan Liang
Life of this patent
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Abstract
A thin film transistor, an array substrate, and a manufacturing method thereof. The manufacturing method comprises: forming a buffer layer and an active layer sequentially on a substrate, and forming an active region through a patterning process; forming a gate insulating layer and a gate electrode sequentially; forming Ni deposition openings; forming a dielectric layer having source/drain contact holes in a one-to-one correspondence with the Ni deposition openings; and forming source/drain electrodes which are connected with the active region via the source/drain contact holes and the Ni deposition openings.
Claims15
A manufacturing method of a thin film transistor, comprising steps of:
- forming a buffer layer and an active layer sequentially on a substrate, and forming an active region through a patterning process on the active layer;
- forming a gate insulating layer and a gate electrode sequentially;
- forming Ni deposition openings;
- forming a dielectric layer having source/drain contact holes in a one-to-one correspondence with the Ni deposition openings;
- and
- forming source/drain electrodes which are connected with the active region via the source/drain contact holes and the Ni deposition openings.
A manufacturing method of an array substrate, comprising steps of:
- forming a buffer layer and an active layer sequentially on a substrate, and forming an active region through a patterning process on the active layer;
- forming a gate insulating layer and a gate electrode sequentially;
- forming Ni deposition openings;
- forming a dielectric layer having source/drain contact holes in a one-to-one correspondence with the Ni deposition openings;
- forming source/drain electrodes which are connected with the active region via the source/drain contact holes and the Ni deposition openings;
- and
- forming a pixel defining and insulating layer so as to form a pixel array.
A thin film transistor, comprising:
- a buffer layer and an active region sequentially formed on a substrate;
- a gate insulating layer having Ni deposition openings, a gate electrode, and a dielectric layer having source/drain contact holes which are sequentially overlaid on the buffer layer and the active region, and the source/drain contact holes being in a one-to-one correspondence with the Ni deposition openings;
- and
- source/drain electrodes connected with the active region via the source/drain contact holes and the Ni deposition openings.
(canceled)
Dependencies are inferred from the claim text.