Stress-reduced circuit board and method for forming the same
AssigneeTong Hsing Electronic Industries, Ltd.
InventorsChien-Cheng Wei, Wu-Hui Cheng
Life of this patent
Estimating the term…
Abstract
A stress-reduced circuit board includes an insulating substrate, and first and second electrically conductive layers which are stacked one upon the other, and which respectively have peripheral marginal regions that are configured in a stepped arrangement. The first electrically conductive layer is configured to have an area dimension larger than that of the second electrically conductive layer and a thickness not greater than that of the second electrically conductive layer so as to minimize stress caused by a difference in coefficients of thermal expansion between the insulating substrate and the first and second electrically conductive layers.
Claims16
A circuit board comprising:
- an insulating substrate;
- and
- an electrically conductive unit including a first electrically conductive layer formed on said insulating substrate, and a second electrically conductive layer stacked on said first electrically conductive layer, said first and second electrically conductive layers respectively having peripheral marginal regions which are configured in a stepped arrangement such that said first electrically conductive layer is configured to have an area dimension larger than that of said second electrically conductive layer, and a thickness not greater than that of said second electrically conductive layer, so as to minimize stress caused by a difference in coefficients of thermal expansion between said electrically conductive unit and said insulating substrate.
A method for forming a stress-reduced circuit board comprising the steps of:
- (A) forming a first electrically conductive layer on an insulating substrate;
- (B) forming a second photoresist layer to cover the first electrically conductive layer;
- (C) patterning the second photoresist layer to form a second cavity which extends from an upper surface of the second photoresist layer to terminate at and expose a first central area of the first electrically conductive layer;
- (D) electroplating a second electrically conductive layer on the first central area of the first electrically conductive layer to fill the second cavity so as to permit an upper surface of the second electrically conductive layer to be substantially flush with the upper surface of the second photoresist layer, such that a peripheral marginal region of the first electrically conductive layer and a peripheral marginal region of the second electrically conductive layer are in a stepped relationship, and such that the first electrically conductive layer has an area dimension larger than that of the second electrically conductive layer, and a thickness not greater than that of the second electrically conductive layer;
- and
- (E) removing the second photoresist layer.
A method for forming a circuit board that includes an insulating substrate and an electrically conductive unit which has a first electrically conductive layer formed on the insulating substrate, and a second electrically conductive layer stacked on the first electrically conductive layer, and which is configured to have a predetermined height, the method comprising the steps of:
- (a) providing an electrically conductor plate that is bonded to the insulating substrate, and that has a height substantially equal to the predetermined height;
- (b) forming a second photoresist layer on an upper surface of the electrically conductor plate;
- (c) patterning the second photoresist layer to expose a second predetermined looped region of the upper surface of the electrically conductor plate;
- (d) etching the second predetermined looped region to define a marginal edge of a peripheral marginal region of the second electrically conductive layer, and to expose a peripheral marginal region of the first electrically conductive layer;
- (e) removing the second photoresist layer;
- (f) forming a first photoresist layer on the upper surface of the electrically conductor plate;
- (g) patterning the first photoresist layer to expose a first predetermined looped region of the upper surface of the electrically conductor plate, the first predetermined looped region surrounding the second predetermined looped region;
- (h) etching the first predetermined looped region to define a marginal edge of the peripheral marginal region of the first electrically conductive layer, and to expose the insulating substrate, such that the peripheral marginal regions of the first and second electrically conductive layers are in a stepped relationship, and such that the first electrically conductive layer has an area dimension larger than that of the second electrically conductive layer, and a thickness not greater than that of the second electrically conductive layer;
- and
- (i) removing the first photoresist layer.
Dependencies are inferred from the claim text.