# US 2014/0089560 A1 · Memory devices and methods having write data permutation for cell wear reduction

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- Number: US 2014/0089560 A1
- Document ID: US20140089560A1
- Status: Published application
- Kind: A1
- Application number: 13/626,721
- Filed: 2012-09-25
- Published: 2014-03-27
- Earliest claimed: 2012-09-25
- Assignees: Adesto Technologies Corporation
- Inventors: Ravi Sunkavalli; Malcolm Wing
- Web page: https://patentgrep.com/patent/US20140089560A1

## CPC

- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 11/00: Error detection; Error correction; Monitoring (error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00)
- G06F 11/1072: {in multilevel memories}
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 7/1012: {Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating}
- G11C 11/56: using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 11/5678: {using amorphous/crystalline phase transition storage elements}
- G11C 13/0002: {using resistive RAM [RRAM] elements}
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/0033: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 16/349: {Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles}
- G11C 29/82: {for EEPROMs}
- G11C 2211/5649: Multilevel memory with plate line or layer, e.g. in order to lower programming voltages
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory system can include a plurality of memory elements each comprising a memory layer having at least one layer programmable between at least two different impedance states; a data input configured to receive multi-bit write data values; and a permutation circuit coupled between the memory elements and the data input, and configured to repeatedly permute the multi-bit write data values prior to writing such data values into the memory elements.

## Claims

### Claim 1

A memory system, comprising:
a plurality of memory elements each comprising a memory element having at least one layer programmable between at least two different impedance states;
a data input configured to receive multi-bit write data values; and
a permutation circuit coupled between the memory elements and the data input, and configured to repeatedly permute the multi-bit write data values prior to writing such data values into the memory elements.

### Claim 2 (depends on 1)

The memory system of claim 1, wherein:
the permutation circuit comprises bit-shift circuits configured to shifts bit positions in a predetermined direction for different permutation types.

### Claim 3 (depends on 1)

The memory system of claim 1, further including:
a wear monitor circuit configured to generate wear indications in response to predetermined wear conditions; and
the permutation circuit is configured to alter a permutation type in response to at least one wear indication.

### Claim 4 (depends on 3)

The memory system of claim 3, wherein:
the memory elements are organized into a number of blocks; and
the permutation circuit is configured to apply different permutations to different blocks in response to at least one wear indication.

### Claim 5 (depends on 4)

The memory system of claim 4, wherein:
the permutation circuit is configured to advance to a next permutation once all blocks have been subject to a previous permutation.

### Claim 6 (depends on 1)

The memory system of claim 1, further including:
a wear monitor circuit configured to generate wear indications in response to predetermined wear conditions; and
the permutation circuit is configured to assign one permutation type to addresses in a first range, and another permutation type to addresses in a second range; wherein
the first and second address ranged change in response to the wear indications.

### Claim 7 (depends on 6)

The memory system of claim 6, further including:
the memory elements are physically organized into a number of blocks; and
an address translation circuit configured to selectively isolate at least one block from accesses according to a particular order, so that each block functions as a spare block in a wear rotation; wherein
the first address range comprises blocks having a physical address less than the at least one spare block, and the second address range comprises blocks having a physical address greater than the at least one spare block.

### Claim 8 (depends on 1)

The memory system of claim 1, wherein:
the permutation circuit comprises bit scramble circuits configured to scramble bit positions in according to key values.

### Claim 9 (depends on 1)

The memory system of claim 1, further including:
an error circuit configured to generate an error code comprising at least one bit in response to received multi-bit write data values; and
the permutation circuit is configured to permute bit positions of the error code and the corresponding write data value.

### Claim 10

A method, comprising:
permuting bits of write data written into memory cells having at least one programmable impedance layer; and
repeatedly changing a permutation type in response to a wear limit for at least a portion of the memory cells.

### Claim 11 (depends on 10)

The method of claim 10, wherein:
permuting bits is selected from the group of: shifting bit positions in a predetermined direction, scrambling bit positions in response to key values, encoding m-bit values into larger n-bit values, and writing m-bit values into larger n-bit locations, with some of the n-bits being unused spare locations.

### Claim 12 (depends on 10)

The method of claim 10, wherein:
permuting bits includes applying different permutation types to different memory cell address ranges.

### Claim 13 (depends on 10)

The method of claim 10, wherein:
permuting bits includes mixing data bit positions with bit positions of a corresponding error code; wherein
the error code is selected from the group of: an error detection code used to detect an error in a data value and an error correction value used to correct an error in a data value.

### Claim 14 (depends on 10)

The method of claim 10, wherein:
the memory cells are organized into blocks; and
permuting bits includes permuting bits on a block-by-block basis.

### Claim 15 (depends on 14)

The method of claim 14, further including:
sequentially designating at least one block as a spare block that is not accessed for read and write operations; and
permuting bits includes
applying one permutation type to blocks having physical addresses below that of a current spare block, and
applying another permutation type to blocks having physical addresses above that a current spare block.

### Claim 16 (depends on 10)

The method of claim 10, wherein:
changing the permutation type includes changing the permutation type applied to at least one group of memory cells in response to a wear indication corresponding to the group of memory cells.

### Claim 17

A memory system, comprising:
a plurality of memory elements each comprising a memory layer having at least one memory layer programmable between at least two different impedance states;
a permutation circuit configured to permute bits of write data written into the memory elements in response to permutation select data; and
a nonvolatile store to store the permutation select data.

### Claim 18 (depends on 17)

The memory system of claim 17, further including:
a monitor circuit configured to generate different permutation select values in response to wear of the memory device, and write a current permutation value into the nonvolatile store.

### Claim 19 (depends on 17)

The memory system of claim 17, wherein:
the permutation circuit comprises a plurality bit mapping circuits, each bit mapping circuit receiving write data values of m-bits, and outputting permuted write data values of m-bits having bit positions that vary from the write data in response to the permutation select data.

### Claim 20 (depends on 17)

The memory system of claim 17, wherein:
the permutation circuit comprises a plurality bit mapping circuits, each bit mapping circuit receiving write data values of m-bits, and outputting permuted write data values of n-bits having bit positions that vary from the write data in response to the permutation select data, where n>m.