Arithmetic circuit for performing division based on restoring division

A processor, comprising:

• an arithmetic circuit configured to perform division based on restoring division;
• and
• an instruction control unit configured to decode an instruction for the division,
• wherein the arithmetic circuit includes:
• an intermediate remainder register configured to store an intermediate remainder;
• a quotient prediction circuit configured to perform, based on information about two most significant digits of the intermediate remainder and a most significant digit of a divisor, quotient prediction having lower precision than a highest precision obtainable from the information, thereby generating a prediction result;
• a fixed-value multiplication circuit configured to output one or more N-th (N:
• integer) multiples of the divisor selected in response to the prediction result generated by the quotient prediction circuit;
• one or more subtracters configured to subtract, from the intermediate remainder, the one or more N-th multiples of the divisor output from the fixed-value multiplication circuit;
• and
• a partial quotient calculating circuit configured to obtain a partial quotient in response to one or more carry-out bits of one or more subtractions performed by the one or more subtracters.

A division method in an arithmetic circuit for performing division based on restoring division, comprising:

• performing, based on information about two most significant digits of an intermediate remainder and a most significant digit of a divisor, quotient prediction having lower precision than a highest precision obtainable from the information, thereby generating a prediction result;
• subtracting, from the intermediate remainder, one or more N-th (N:
• integer) multiples of the divisor selected in response to the prediction result;
• and
• obtaining a partial quotient in response to one or more carry-out bits obtained from the subtracting.