Semiconductor device and data processing system including the same
AssigneeElpida Memory, Inc.
InventorHiroto KINOSHITA
Life of this patent
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Abstract
To provide a write amplifier that is connected to bit lines, a read amplifier that is connected to the bit lines via a first switch, and a relief memory element that includes a write port that is connected to the bit lines via a second switch, and a read port that is connected to the read amplifier via a third switch. When there is a request to access a defective memory cell, during a write operation, the second switch is turned on and write data is supplied from the write amplifier to the relief memory element via the bit lines, and during a read operation, the first switch is turned off and the third switch is turned on, and then read data read from the relief memory element is supplied to the read amplifier without being routed via the bit lines.
Claims6
A semiconductor device comprising:
- a plurality of memory arrays each including a plurality of memory cells;
- a plurality of input/output lines each provided for an associated one of the memory arrays, each of the input/output lines being operatively coupled to a selected one of the memory cells of an associated one of the memory arrays;
- a bus line;
- a plurality of write amplifiers, each of write amplifiers being configured to drive, when activated, an associated one of the input/output lines in response to a first data signal supplied from the bus line;
- a plurality of read amplifiers each including an input port, each of the read amplifiers being configured to drive, when activated, the bus line in response to a second data signal supplied to the input port;
- a plurality of relief memory elements;
- a plurality of first switch circuits, each of the first switch circuits being connected between an associated one of the input/output lines and the input port of an associated one of the read amplifiers;
- a plurality of second switch circuits, each of the second switch circuits being connected between an associated one of the input/output lines and an associated one of the relief memory elements;
- and
- a plurality of third switch circuits, each of the third switch circuits being connected between an associated one of the relief memory elements and the input port of an associated one of the read amplifiers.
Dependencies are inferred from the claim text.