Pixel clock generator, method of operating the same, and apparatuses including the pixel clock generator
AssigneeSamsung Electronics Co., Ltd.
InventorsSung Jin KIM, Tae Ik KIM, Se Hyung JEON
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Abstract
A method of operating a pixel clock generator (PCG), the method including generating N clock signals according to a control voltage signal, the N clock signals having different phases and N being a natural number; generating M frequency-divided clock signals based on the N clock signals, the M frequency-divided clock signals having different phases and M being a natural number greater than N; and generating a pixel clock signal based on at least two selected ones of the M frequency-divided clock signals.
Claims16
-5. (canceled)
The PCG of claim 5, wherein the pixel clock signal modulator comprises:
- a first frequency dividing circuit configured to divide frequencies of the at least two selected frequency-divided clock signals and generate at least two twice-frequency-divided clock signals;
- and
- a clock modulation circuit configured to generate the pixel clock signal based on the at least two twice-frequency-divided clock signals output from the first frequency dividing circuit.
The PCG of claim 5, wherein the natural number M is an integer multiple of the natural number N.
The PCG of claim 5, wherein the frequency-divided multiphase signal generating circuit comprises:
- a plurality of D flip-flops, a first one of the plurality of D flip-flops having,
- an output terminal connected to a clock terminal of a second one of the plurality of D flip-flops, and
- an inverted output terminal connected to both an input terminal of the first one of the plurality of D flip-flops and a clock terminal of a third one of the plurality of D flip-flops.
An analog front-end (AFE) comprising:
- the pixel clock generator (PCG) of claims 5;
- and
- an analog-to-digital converter (ADC) configured to convert an analog image signal into a digital image signal based on the pixel clock signal.
A pixel clock generator (PCG) comprising:
- a multiphase signal generator configured to generate frequency-divided clock signals according to a received horizontal synchronization signal, the frequency-divided clock signals each having a different phase;
- and
- a pixel clock signal modulator configured to generate a pixel clock signal and a frequency-divided pixel clock signal based on at least two of the frequency-divided clock signals.
Dependencies are inferred from the claim text.