System and method to provide single thread access to a specific memory region
AssigneeIntel Corporation
InventorNicholas J. ADAMS
Life of this patent
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Abstract
Processing logic and a method to provide single thread access to a specific memory region without suspending processing activity for all other cores and/or threads within or in association with a processor, computer system, or other processing apparatus. Single thread access may be provided through implementation of microcode which may control thread access to model specific registers (“MSRs”) within a processor. One MSR may provide a mutex, which a single thread may claim, and another MSR may provide a range of memory locations, which may be accessed by the thread that has claimed the mutex.
Claims27
A processor, comprising:
- a first memory location to store a mutex, possession of the mutex by one of a plurality of requesters to enable read/write access to a predetermined range of second memory locations for a mutex possessing requester;
- logic to allow mutex possession by a requester if the mutex is available;
- logic to deny mutex possession by a requester if the mutex is unavailable;
- logic to disable read/write access to the predetermined range of second memory locations for a requester not in possession of the mutex, the circuitry to return a predetermined error code to the non-possessing requester for attempts by the non-possessing requester to access the predetermined range of second memory locations;
- logic to release possession of the mutex by a mutex possessing requestor upon completion of a processing task by the mutex possessing requester.
A non-transitory machine-readable medium having stored thereon data, which if executed by a processor, causes the processor to perform a method, the method comprising:
- allocating a predetermined range of memory locations, the memory locations including a first memory location to provide storage for a mutex token and a plurality of second memory locations, each to provide temporary data storage;
- reading, by a requester attempting to access the plurality of second memory locations, the first memory location to determine availability of the mutex;
- if the mutex is available,
- allowing possession of the mutex by the requester;
- enabling read/write access to the requester to the plurality second memory locations;
- and
- if the mutex is unavailable, denying possession of the mutex by the requester.
A method, comprising:
- allocating a predetermined range of memory locations within a processor, the memory locations including a first memory location to provide storage for a mutex token and a plurality of second memory locations, each to provide temporary data storage;
- reading, by a requester attempting to access the plurality of second memory locations, the first memory location to determine availability of the mutex;
- if the mutex is available,
- allowing possession of the mutex by the requester;
- enabling read/write access to the requester to the plurality second memory locations;
- and
- if the mutex is unavailable, denying possession of the mutex by the requester.
A system, comprising:
- system memory to store at least one of instructions and data;
- a processor coupled to said system memory, said processor including
- a first memory location to store a mutex, possession of the mutex by one of a plurality of requesters to enable read/write access to a predetermined range of second memory locations for a mutex possessing requester;
- logic to allow mutex possession by a requester if the mutex is available;
- logic to deny mutex possession by a requester if the mutex is unavailable;
- logic to disable read/write access to the predetermined range of second memory locations for a requester not in possession of the mutex, the circuitry to return a predetermined error code to the non-possessing requester for attempts by the non-possessing requester to access the predetermined range of second memory locations;
- logic to release possession of the mutex by a mutex possessing requestor upon completion of a processing task by the mutex possessing requester.
Dependencies are inferred from the claim text.