Monitoring accesses of a thread to multiple memory controllers and selecting a thread processor for the thread based on the monitoring

An apparatus comprising:

• a plurality of thread processors to run a plurality of threads;
• a first memory controller coupled with the plurality of thread processors, the first memory controller to couple with and provide access to a first memory;
• a second memory controller coupled with the plurality of thread processors, the second memory controller to couple with and provide access to a second memory;
• a memory controller access monitor unit coupled with a first thread processor of the plurality, the memory controller access monitor unit to monitor accesses, by a thread of the plurality that is running on the first thread processor, to both the first memory controller and the second memory controller;
• a thread processor selector unit coupled with the memory controller access monitor unit, the thread processor selector unit to select a second thread processor of the plurality for a thread based on the monitoring of the accesses by the thread to both the first memory controller and the second memory controller.

A system comprising:

• a first memory;
• a second memory;
• a first memory controller coupled with the first memory to provide access to the first memory;
• a second memory controller coupled with the second memory to provide access to the second memory;
• a plurality of thread processors coupled with the first and second memory controllers, the thread processors to run a plurality of threads that access the first and second memories through the first and second memory controllers;
• and
• an operating system module stored in a memory, the operating system module to install a thread on a thread processor based at least in part on a relative proportion of accesses by the thread to both the first and second memories.