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US 2014/0007037 A1Published application
Estimating optimal gate sizes by using numerical delay models
AssigneeSynopsys, Inc.
InventorsAmir H. Mottaez, Mahesh A. Iyer
Life of this patent
Estimating the term…
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AssigneeSynopsys, Inc.
InventorsAmir H. Mottaez, Mahesh A. Iyer
Estimating the term…
Systems and techniques are described for estimating optimal gate sizes in a circuit design using numerical delay models of cells and cell types in a technology library. Gate sizes are optimized in the circuit design in a reverse-levelized processing order. Gates that are at the same level in the reverse-levelized processing order, and whose inputs are electrically connected to the same driver output are optimized together. A closed-form expression is used to determine the optimized size for each gate in a set of gates that are optimized together. Some embodiments perform multiple optimization iterations, wherein in each optimization iteration all of the gates in the circuit design are processed in the reverse-levelized processing order. The iterative optimization process terminates when one or more termination conditions are met.
A method for optimizing a circuit design, the method comprising:
A non-transitory computer-readable storage-medium storing instructions that, when executed by a computer system, cause the computer system to perform a method for optimizing a circuit design, the method comprising:
A computer system, comprising:
Dependencies are inferred from the claim text.