Method and Apparatus to Perform Footprint-Based Optimization Simultaneously with Other Steps
AssigneeSynopsys, Inc.
InventorsBarry David Turner, JR., Cristian Eugen Golovanov, Henry Shiu-Wen Sheng
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Abstract
A method comprising placing elements in a layout, performing clock tree synthesis, and performing routing. The method further comprising, in parallel with one of the clock tree synthesis or the routing, performing a footprint based optimization, substituting a footprint equivalent element in a path based on a timing slack of the path.
Claims19
A method comprising:
- by using at least one computer, placing cells in a layout;
- performing clock tree synthesis to generate clock signals for an integrated circuit including the cells;
- performing routing to route signals for the integrated circuit;
- and
- in parallel with the routing, performing a footprint based optimization, substituting a cell with a footprint equivalent cell in a path based on a timing slack of the path, wherein the performing of the footprint based optimization comprises (i) evaluating the timing slack of the path and (ii) selecting the footprint equivalent cell based on a type and size of the timing slack.
8-12. (canceled)
A system comprising:
- at least one processor;
- an integrated circuit design element comprising:
- a layout logic to place cells;
- a clock tree synthesis logic to generate clock signals for an integrated circuit including the cells;
- and
- a routing logic to route signals for the integrated circuit;
- and
- a footprint-based optimization element comprising:
- a slack evaluation system to evaluate slack in a path;
- and
- a cell substitution logic to select a footprint equivalent cell for replacing a cell in the path, based on a type and size of the slack,
- wherein the footprint-based optimization element operates in parallel with the routing logic of the integrated circuit design element.
A computer program product stored as program code on a non-transitory computer-readable medium, the program code executable by at least one processor to reduce processing time in circuit design, the computer program product comprising a computer readable program code comprising instructions for:
- placing cells in a layout;
- performing clock tree synthesis to generate clock signals for an integrated circuit including the cells;
- performing routing to route signals for the integrated circuit;
- and
- performing, in parallel with the routing, a footprint based optimization by substituting a cell with a footprint equivalent cell in a path based on a timing slack of the path, wherein the performing of the footprint based optimization comprises (i) evaluating the timing slack of the path and (ii) selecting the footprint equivalent cell based on a type and size of the timing slack.
Dependencies are inferred from the claim text.