Routing of local clock interconnects

A computer usable program product comprising a computer usable storage medium including computer usable code for improved routing of local clock interconnects in an integrated circuit (IC) design, the computer usable code comprising:

• computer usable code for selecting, from a set of endpoints in the IC design, an endpoint, wherein the endpoint is an electronic component represented in the IC design, and includes a representation of a pin at which an electrical connection in the IC design can be configured;
• computer usable code for calculating an original delay in a segment in a route that supplies a clock signal to the pin;
• computer usable code for adding, responsive to the original delay exceeding a delay threshold, a cross-link in the route such that the cross-link completes a non-tree sub-network including the segment, wherein the non-tree sub-network is a part of a non-tree network of interconnects carrying the clock signal in the IC design;
• computer usable code for calculating, using a processor and a memory, a revised delay in the segment without using delay information corresponding to another non-tree sub-network in the non-tree network, wherein the calculating the revised delay includes virtually manipulating the non-tree sub-network such that the revised delay can be computed in the manner of computing delay of a tree network;
• and
• computer usable code for modifying the route using the revised delay in the segment such that at least one of (i) a clock skew at the pin is reduced, (ii) a power dissipation of clock distribution is reduced, (iii) a maximum clock skew in the IC design is reduced, (iv) a size of clock network is reduced, (v) a clock jitter in the IC design is reduced, and (vi) a maximum clock latency in the IC design is reduced.

A data processing system for improved routing of local clock interconnects in an integrated circuit (IC) design, the data processing system comprising:

• a storage device including a storage medium, wherein the storage device stores computer usable program code;
• and
• a processor, wherein the processor executes the computer usable program code, and wherein the computer usable program code comprises:
• computer usable code for selecting, from a set of endpoints in the IC design, an endpoint, wherein the endpoint is an electronic component represented in the IC design, and includes a representation of a pin at which an electrical connection in the IC design can be configured;
• computer usable code for calculating an original delay in a segment in a route that supplies a clock signal to the pin;
• computer usable code for adding, responsive to the original delay exceeding a delay threshold, a cross-link in the route such that the cross-link completes a non-tree sub-network including the segment, wherein the non-tree sub-network is a part of a non-tree network of interconnects carrying the clock signal in the IC design;
• computer usable code for calculating, using a processor and a memory, a revised delay in the segment without using delay information corresponding to another non-tree sub-network in the non-tree network, wherein the calculating the revised delay includes virtually manipulating the non-tree sub-network such that the revised delay can be computed in the manner of computing delay of a tree network;
• and
• computer usable code for modifying the route using the revised delay in the segment such that at least one of (i) a clock skew at the pin is reduced, (ii) a power dissipation of clock distribution is reduced, (iii) a maximum clock skew in the IC design is reduced, (iv) a size of clock network is reduced, (v) a clock jitter in the IC design is reduced, and (vi) a maximum clock latency in the IC design is reduced.