Device for and method of generating wiring data, and imaging system

An imaging system that directly exposes a substrate placed on a stage, the imaging system comprising:

• a device for generating wiring data indicating a connection wiring pattern extending over a substrate from each electrode of a semiconductor chip placed on said substrate;
• an optical head unit that directly exposes said substrate without using a mask for exposure;
• a stage that holds said substrate thereon, and moves relative to said optical head unit;
• a photographing part that photographs said semiconductor chip placed on said substrate;
• and
• an imaging data generating part that generates imaging data rasterized for the imaging system, wherein
• said device includes:
• an error acquiring part that acquires a configuration error of said semiconductor chip relative to a certain reference position and a certain reference angle on said substrate;
• an area information acquiring part that acquires enclosing area information indicating an enclosing area enclosing said semiconductor chip on said substrate;
• and
• a wiring data generating part that generates enclosing area wiring data indicating an enclosing area wiring pattern based on a reference fan-out line established for a reference chip, the enclosing area wiring pattern being a part of said connection wiring pattern and covering said enclosing area,
• said reference chip expresses the condition of said semiconductor chip placed in said reference position and said reference angle on said substrate,
• a reference wiring pattern free from faulty wiring is assigned to said reference chip as a pattern corresponding to said connection wiring pattern,
• said reference fan-out line is a part of said reference wiring pattern and routed on said reference chip,
• said wiring data generating part generates said enclosing area wiring data such that the position and the angle of said reference fan-out line relative to said reference chip, and the position and the angle of a fan-out line for said semiconductor chip on said substrate relative to this semiconductor chip, agree with each other independently of said configuration error,
• in said device, said error acquiring part acquires said configuration error based on an image of said semiconductor chip formed by said photographing part, and said wiring data generating part generates said enclosing area wiring data based on said configuration error,
• said imaging data generating part generates said imaging data based on said enclosing area wiring data generated by said device, and
• said imaging system makes said optical head unit directly expose said substrate placed on said stage based on said imaging data generated by said imaging data generating part.

A method of generating wiring data indicating a connection wiring pattern extending over a substrate from each electrode of a semiconductor chip placed on said substrate, the method comprising the steps of:

• (a) acquiring a configuration error of said semiconductor chip relative to a certain reference position and a certain reference angle on said substrate;
• (b) acquiring enclosing area information indicating an enclosing area enclosing said semiconductor chip on said substrate;
• and
• (c) generating enclosing area wiring data indicating an enclosing area wiring pattern based on a reference fan-out line established for a reference chip, the enclosing area wiring pattern being a part of said connection wiring pattern and covering said enclosing area, wherein
• said reference chip expresses the condition of said semiconductor chip placed in said reference position and said reference angle on said substrate,
• a reference wiring pattern free from faulty wiring is assigned to said reference chip as a pattern corresponding to said connection wiring pattern,
• said reference fan-out line is a part of said reference wiring pattern and routed on said reference chip, and
• in said step (c), said enclosing area wiring data is generated such that the position and the angle of said reference fan-out line relative to said reference chip, and the position and the angle of a fan-out line for said semiconductor chip on said substrate relative to this semiconductor chip, agree with each other independently of said configuration error.