Method for analyzing placement context sensitivity of standard cells
AssigneeFreescale Semiconductor, Inc.
InventorsRobert E. Boone, Puneet Sharma, Matthew A. Thompson
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AssigneeFreescale Semiconductor, Inc.
InventorsRobert E. Boone, Puneet Sharma, Matthew A. Thompson
Estimating the term…
A disclosed method for evaluating placement context sensitivity in the design of an integrated circuit includes accessing a standard cell library comprising a database of standard cells and determining generating boundary data for each of the standard cells. The boundary data for a standard cell indicates the layout of features located within boundary regions of the standard cell. The method includes merging or consolidating boundary data for any two standard cells if their boundary data is the same to determine a canonical or minimal set of boundary regions. The disclosed method further includes enumerating and evaluating all combinations of pairs of the canonical boundary regions and, responsive to identifying of a proximity-based sensitivity or exception, modifying, notating, or otherwise remediating the applicable one or more standard cells that correspond to the boundary region combination that raised the exception.
An integrated circuit design method, comprising:
The method of claim 8, wherein the constraining prevents placement of standard cells possessing the first boundary structure adjacent and to the left of standard cells possessing the second boundary structure.
11-15. (canceled)
A non-transitory computer readable medium including processor-executable program instructions comprising instructions for:
A data processing system, comprising:
Dependencies are inferred from the claim text.