Memory device

A memory device, comprising:

• a memory chip that stores data;
• and
• an external controller that controls the memory chip,
• the memory chip comprising:
• a plurality of memory cells configured to store data of two or more bits, the memory cells constituting a page as a program unit;
• and
• an internal controller that executes a program operation for page data including a lower page program operation and an upper page program operation for the same page of the memory cell array, and executes a read operation for page data including a lower page read operation and an upper page read operation from the memory cell array,
• the memory cell array including a normal access area accessible from the external controller, and an LM flag area for storing an LM flag indicating whether the upper page program operation for each page of the normal access area is complete,
• the internal controller being configured to set the LM flag in the upper page program operation, output the page data read from the memory cell array to the external controller, regardless of whether the upper page program operation is complete or not, in the upper page read operation, and output a state of the LM flag corresponding to the read page data to the external controller as status information,
• the external controller including an error correction unit that performs error correction encoding on data to be programmed into the memory cell array and performs error correction decoding on data read from the memory cell array, and being configured to identify whether the read page data is lower page data or upper page data by referring to the status information, after performing the error correction decoding on data read from the memory chip, in the read operation.

A memory device, comprising:

• a memory chip that stores data;
• and
• an external controller that controls the memory chip,
• the memory chip comprising:
• a memory cell array including a plurality of memory cells configured to store data of two or more bits, the memory cells constituting a page as a program unit;
• and
• an internal controller that executes a program operation for page data including a lower page program operation and an upper page program operation for the same page of the memory cell array, and executes a read operation for page data including a lower page read operation and an upper page read operation from the memory cell array,
• the external controller including an error correction unit that performs error correction encoding on data to be programmed into the memory cell array and performs error correction decoding on data read from the memory cell array,
• the internal controller being configured to output the read page data from the memory cell array to the external controller, regardless of whether the upper page program operation is complete or not, in the upper page read operation.