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US 2014/0006901 A1Published application
Memory system
AssigneeSK hynix Inc.
InventorsYoung Suk MOON, Hyung Dong LEE, Yong Kee KWON, Hyung Gyun YANG
Life of this patent
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Abstract
A memory system includes a processor and a plurality of memories. The processor includes a plurality of ECCs having different error restoration rates with each other, and a plurality of memories is coupled to the plurality of ECCs, respectively, according to distances from the processor.
Claims19
A memory system comprising:
- a processor configured to include a plurality of ECCs having different error restoration rates with each other;
- and
- a plurality of memories configured to be coupled to the plurality of ECCs, respectively, according to distances from the processor.
A memory system comprising:
- a processor configured to include a first ECC having a first error restoration rate and a second ECC having a second error restoration rate which is higher than the first error restoration rate;
- a first memory configured to be stacked on top of the processor, and to be coupled to the first ECC;
- and
- a second memory configured to be stacked on top of the first memory, and to be coupled to the second ECC.
1 more element
A memory system comprising:
- a processor configured to perform data input/output communication;
- is a logic die configured to communicate with the processor, and to include a first ECC having a first error restoration rate and a second ECC having a second error restoration rate which is higher than the first error restoration rate;
- a first memory die configured to be stacked on top of the logic die, and to be coupled to the first ECC;
- and
- a second memory die configured to be stacked on top of the first memory die, and to be coupled to the second ECC.
2 more elements
Dependencies are inferred from the claim text.