System and method for aligning data bits
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYing-Yu HSU, Ruey-Bin SHEEN, Shih-Hung LAN, Chih-Hsien CHANG
Life of this patent
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Abstract
Systems and methods are disclosed for aligning multiple data bits by adjusting the timing of input lines for those data bits. Embodiments include a hierarchical structure for comparing the timing of multiple sets of bits. Other embodiments include aligning data bits from multiple chips in a 3D die stacking architecture.
Claims20
A method for aligning plural data bits where each data bit has an associated leading edge, the method comprising the steps of:
- (a) receiving at a first circuit device N1 of the plural data bits via N1 separate input paths, respectively, wherein N1>1;
- (b) determining which of the N1 bits arrives first based on a relative time of arrival of the leading edge of each of the N1 bits;
- and
- (c) adjusting the input path associated with the first-to-arrive N1 bit.
An apparatus for aligning plural data bits where each data bit has an associated leading edge, comprising:
- a first circuit device for receiving N1 of the plural data bits via N1 separate input paths, respectively, wherein N1>1;
- a first comparison circuit for determining which of the N1 bits arrives first at said first circuit device based on a relative time of arrival of the leading edge of each of the N1 bits;
- and
- a first timing adjustment circuit for applying a first adjustment to the input path associated with the first-to-arrive N1 bit.
An apparatus for aligning plural data bits where each data bit has an associated leading edge, comprising:
- a first circuit for determining a first-to-arrive M1 bit of N1 bits wherein each of said N1 bits is associated with a separate input path, and wherein N1>1;
- a second circuit for determining a first-to-arrive M2 bit of N2 bits wherein each of said N2 bits is associated with a separate input path, and wherein said N2 bits are mutually exclusive of said N1 bits, and wherein N2>1;
- a third circuit for determining a first-to-arrive M3 bit of N3 bits wherein each of said N3 bits is associated with a separate input path, and wherein said N3 bits are mutually exclusive of said N1 bits and said N2 bits, and wherein N3>1;
- a fourth circuit for determining a first-to-arrive M4 bit of N4 bits wherein each of said N4 bits is associated with a separate input path, and wherein said N4 bits are mutually exclusive of said N1 bits and said N2 bits and said N3 bits, and wherein N4>1;
- a fifth circuit for determining a first-to-arrive P1 bit of said M1 through M4 bits;
- and
- adjusting an input path associated with said P1 bit.
Dependencies are inferred from the claim text.