No-touch stress testing of memory i/o interfaces
AssigneeIntel Corporation
InventorsSankaran M. Menon, Robert R. Roeder
Life of this patent
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Abstract
Embodiments are generally directed no-touch stress testing of memory input/output (I/O) interfaces. An embodiment of a memory device includes a system element to be coupled with a dynamic random-access memory (DRAM), the system element including a memory interface for connection with the DRAM, the interface including a driver and a receiver, a memory controller for control of the DRAM, and a timing stress testing logic for testing of the I/O interface.
Claims28
An apparatus comprising:
- a system element to be coupled with a dynamic random-access memory (DRAM), the system element including:
- a memory input/output (I/O) interface for connection with the DRAM, the interface including a driver and a receiver,
- a memory controller for control of the DRAM, and
- a timing stress testing logic for testing of the memory I/O interface.
A method comprising:
- commencing a test process for a memory I/O interface;
- generating a test pattern for the memory I/O interface;
- switching a signal path to an I/O interface test path, wherein the signal path may be switched to either the I/O interface test path or a functional path;
- setting one or more delays for the signal path;
- applying the test pattern to the memory I/O interface and detecting an output from the memory I/O interface;
- and
- comparing the output from the memory I/O interface with the test pattern.
A system comprising:
- a processor to process data for the system;
- a transmitter, receiver, or both coupled with an omnidirectional antenna to transmit data, receive data, or both;
- and
- a combined memory device including a system on chip (SoC) and a memory stack including one or more DRAM layers, the memory stack being coupled to SoC by a micro-bump connection, the system element includes a plurality of through silicon vias (TSVs), including a first TSV coupled with a first micro-bump;
- wherein the SoC includes:
- a memory input/output (I/O) interface, the interface including a driver and a receiver,
- a memory controller for control of the DRAM, and
- a timing stress testing logic for testing of the memory I/O interface.
A non-transitory computer-readable storage medium having stored thereon data representing sequences of instructions that, when executed by a processor, cause the processor to perform operations comprising:
- commencing a test process for a memory I/O interface;
- generating a test pattern for the memory I/O interface;
- switching a signal path to an I/O interface test path, wherein the signal path may be switched to either the I/O interface test path or a functional path;
- setting one or more delays for the signal path;
- applying the test pattern to the memory I/O interface and detecting an output from the memory I/O interface;
- and
- comparing the output from the memory I/O interface with the test pattern.
Dependencies are inferred from the claim text.