Test circuit of semiconductor memory apparatus and semiconductor memory system including the same
AssigneeSK hynix Inc.
InventorsHyung Gyun YANG, Hyung Dong LEE, Yong Kee KWON, Young Suk MOON
Life of this patent
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Abstract
A semiconductor memory apparatus includes a test circuit configured to receive a plurality of sequentially-changing test input patterns, compress the received test input patterns at each clock signal, and output the compressed patterns as variable test data.
Claims24
A semiconductor memory apparatus comprising a test circuit configured to receive a plurality of sequentially-changing test input patterns, compress the received test input patterns at each clock signal, and output the compressed patterns as variable test data.
A test circuit of a semiconductor memory apparatus, comprising:
- a plurality of input units configured to receive a plurality of sequentially-changing test input patterns, respectively, during a test mode;
- and
- a compression unit comprising a plurality of XOR gates configured to receive the respective test input patterns received by the input units and a plurality of registers alternately connected to the XOR gates and forming a chain structure, and configured to finally output an output signal of the register positioned at the last stage as test data.
A semiconductor memory system comprising:
- a stacked memory comprising one or more memories;
- a processor configured to control the stacked memory;
- and
- a substrate having the processor and the stacked memory mounted thereon,
- wherein the stacked memory comprises a test circuit configured to receive a plurality of sequentially-changing test input patterns from the processor during a test mode, compress the received patterns at each clock signal, and output the compressed patterns as test data.
A semiconductor memory system comprising:
- a stacked memory comprising one or more memories;
- is a processor configured to control the stacked memory;
- and
- a substrate having the processor and the stacked memory mounted thereon,
- wherein the processor comprises a test circuit configured to receive a plurality of sequentially-changing test input patterns from the substrate during a test mode, compress the received patterns at each clock signal, and output the compressed patterns as variable test data.
Dependencies are inferred from the claim text.