Clock glitch detection circuit
AssigneeFreescale Semiconductor, Inc.
InventorsMichael Rohleder, Thomas Koch, Vladimir Litovtchenko, Thomas Luedeke
Life of this patent
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Abstract
In a first circuit for detecting clock glitches in a clock signal, a master counter is clocked by the clock signal and memorizes a master count. An incrementer advances the master count by one increment. A slave counter is clocked by the clock signal and memorizes a slave count. The slave count is retarded relative to the master count by at least a particular number of clock edges. A comparator determines whether the difference between the master count and the slave count is at least a value of the incrementer times the particular number of clock edges.
Claims20
A synchronous circuit comprising:
- a clock tree configured to transmit a clock signal from a start point to one or more other points, wherein the start point and the other points include a first point and second point;
- a first counter clocked by the clock signal at the first point, wherein the first counter is configured to store a first count;
- a first incrementer configured to advance the first count by one increment;
- a second counter clocked by the clock signal at the second point, wherein the second counter is configured to store a second count;
- a second incrementer configured to advance the second count by one increment;
- and
- a comparator configured to determine one of a difference between the first count and the second count or whether the first count and the second count differ.
A synchronous circuit comprising:
- a clock tree configured to transmit a clock signal from a start point to one or more other points, wherein the start point and the other points include a first point and second point;
- a rising-edge counter in communication with the clock tree, the rising-edge counter configured to be triggered by rising edges in the clock signal, and to store a rising-edge count, wherein the rising-edge counter is at the first point;
- a falling-edge counter in communication with the clock tree, the falling-edge counter configured to be triggered by falling edges in the clock signal, and to store a falling-edge count, wherein the falling-edge counter is at the second point;
- and
- a rising-edge incrementer in communication with the rising-edge counter, the rising-edge incrementer configured to advance the rising-edge count by one increment;
- a falling-edge incrementer in communication with the falling-edge counter, the falling-edge incrementer configured to advance the falling-edge count by one increment;
- and
- a comparator in communication with the rising-edge counter and the falling edge counter, the comparator configured to determine a difference between the rising-edge count and the falling edge count, or to determine whether the rising-edge count and the falling edge count differ.
A method comprising
- transmitting, by a clock tree, a clock signal from a start point to one or more other points, wherein the start point and the other points comprising a first point and second point;
- clocking, by the clock signal, a first counter at the first point, wherein the first counter is configured to store a first count;
- advancing, by a first incrementer, the first count by one increment;
- clocking, by the clock signal, a second counter at the second point, wherein the second counter is configured to store a second count;
- advancing, by a second incrementer, the second count by one increment;
- and
- determining one of a difference between the first count and the second count or whether the first count and the second count differ.
Dependencies are inferred from the claim text.