Systems, Apparatuses, and Methods for Performing a Shuffle and Operation (Shuffle-Op)
AssigneeIntel Corporation
InventorsIgor Ermolaev, Elmoustapha Ould-Ahmed-Vall, Brett Toll, Andrey Naraikin, Jesus Corbal
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Abstract
Embodiments of systems, apparatuses, and methods for performing in a computer processor a data element shuffle and an operation on the shuffled data elements in response to a single data element shuffle and an operation instruction that includes a destination vector register operand, a first and second source vector register operands, an immediate value, and an opcode are described.
Claims20
A method of performing in a computer processor a data element shuffle and an operation on the shuffled data elements in response to a single data element shuffle and an operation instruction that includes a destination vector register operand, a first and second source vector register operands, an immediate value, and an opcode, the method comprising steps of:
- executing the single data element shuffle and an operation instruction to shuffle data elements of the first source register by a number of data elements wherein the number of data elements is defined by the immediate of the instruction and perform the operation defined by the opcode on the shuffled data elements of the first source vector register with non-shuffled data elements of the second source vector register;
- and
- storing a result of each operation in a corresponding packed data element position of the destination vector register.
An article of manufacture comprising:
- a tangible machine-readable storage medium having stored thereon an occurrence of an instruction, wherein the instruction's format specifies as its first source operand a first vector register, as its second source operand a second vector register, as its destination a single destination vector register, and includes an immediate value, wherein the instruction format includes an opcode which instructs a machine, responsive to the single occurrence of the single instruction, to cause shuffling of data elements of the first source register by a number of data elements wherein the number of data elements is defined by the immediate and performing of the operation defined by the opcode on the shuffled data elements of the first source vector register with non-shuffled data elements of the second source vector register;
- and
- storing a result of each operation in a corresponding packed data element position of the destination vector register.
An apparatus comprising;
- a hardware decoder to decode a data element shuffle and operation instruction, the data element shuffle and operation instruction including a destination vector register operand, a first and second source vector register operands, an immediate value, and an opcode;
- execution logic to execute the data element shuffle and an operation instruction to shuffle data elements of the first source register by a number of data elements wherein the number of data elements is defined by the immediate of the instruction and perform the operation defined by the opcode on the shuffled data elements of the first source vector register with non-shuffled data elements of the second source vector register, and store a result of each operation in a corresponding packed data element position of the destination vector register.
Dependencies are inferred from the claim text.