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US 2014/0006755 A1Published application
Vector multiplication with accumulation in large register space
AssigneeIntel Corporation
InventorsShay Gueron, Vlad Krasnov, Robert Valentine, Zeev Sperber, Amit Gradstein, Simon Rubanovich
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Abstract
An apparatus is described having an instruction execution pipeline that has a vector functional unit to support a vector multiply add instruction. The vector multiply add instruction to multiply respective K bit elements of two vectors and accumulate a portion of each of their respective products with another respective input operand in an X bit accumulator, where X is greater than K.
Claims20
An apparatus, comprising:
- an instruction execution pipeline having a vector functional unit to support a vector multiply add instruction, said vector multiply add instruction to multiply respective K bit elements of two vectors and accumulate a portion of each of their respective products with another respective input operand in an X bit accumulator, where X is greater than K.
A method, comprising:
- accepting a multiplicand operand and a multiplier operand from first and second registers, said multiplier operand and said multiplicand operand being elements of a first vector and a second vector respectively and submitted for a vector processing instruction, said registers being wider than a maximum permissible size of said multiplicand operand and said multiplier operand;
- multiplying said multiplicand operand and said multiplier operand to produce a multiplication result;
- using said first and second registers to provide operands for another vector processing instruction where at least one of said operands is wider than said maximum permissible size.
A computing system, comprising:
- a processing core comprising an instruction execution pipeline, said instruction execution pipeline including:
- i) a first vector execution unit, said first vector execution unit to perform vector multiplication, said first vector execution unit coupled to receive vector operands, said vector execution unit having a multiplier that provides a maximum number of significant digits in performing said vector multiplication for a particular vector element location, wherein one half of said maximum number of significant digits is less than an amount of register space provided for elements of vectors processed by said instruction execution pipeline;
- ii) a first integer execution unit, said first integer execution unit having a second multiplier having at least a substantially same design as said multiplier.
Dependencies are inferred from the claim text.