Qualifying Software Branch-Target Hints with Hardware-Based Predictions

A method to qualify software target-branch hints with hardware-based predictions, the method comprising:

• decoding an indirect branch instruction having an instruction address;
• computing a target address of the indirect branch instruction;
• accessing a branch target address cache to determine if an entry has a stored address value matching the instruction address;
• provided there is a match, determining a state value stored in the entry, the state value belonging to a set, the entry having a stored target value;
• using the stored target value as the predicted target address for the indirect branch instruction only if the state value belongs to a proper subset of the set.

A processor to qualify software target-branch hints with hardware-based predictions, the processor comprising:

• means for decoding an indirect branch instruction having an instruction address;
• means for accessing a branch target address cache to determine if an entry has a stored address value matching the instruction address;
• provided there is a match, means for determining a state value stored in the entry, the state value belonging to a set, the entry having a stored target value;
• means for using the stored target value as the predicted target address for the indirect branch instruction only if the state value belongs to a proper subset of the set.