Mirroring memory commands to memory devices
AssigneeIntel Corporation
InventorsChristopher E. Cox, Rebecca Z. Loop, Christopher P. Mozak
Life of this patent
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Abstract
In one embodiment, a system on a chip (SoC) includes a plurality of processor cores and a memory controller to control communication between the SoC and a memory coupled to the memory controller. The memory controller may be configured to send mirrored command and address signals to a first type of memory device and to send non-mirrored control and address signals to a second type of memory device. Other embodiments are described and claimed.
Claims29
An apparatus comprising:
- system on a chip (SoC) including a plurality of processor cores and a memory controller to control communication between the SoC and a memory coupled to the memory controller, the memory controller to send mirrored command and address signals to a first type of memory device and to send non-mirrored control and address signals to a second type of memory device.
A method comprising:
- determining if a memory coupled to a processor is operating in a mirrored memory mode;
- if so, communicating mirrored command and address signals to a first unit of the memory via a first portion of command and address connections of the processor and a first point-to-point (PtP) memory interconnect, and communicating the mirrored command and address signals to a second unit of the memory via a second portion of the command and address connections of the processor and a second PtP memory interconnect;
- and
- otherwise communicating non-mirrored command and address signals to the first and second units of the memory via at least a portion of the command and address connections and a multi-drop memory interconnect.
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An apparatus comprising:
- a memory module to operate according to a low power memory protocol, the memory module including a plurality of memory devices, wherein the memory module is to receive mirrored command signals on a first point-to-point (PtP) memory interconnect and a second PtP memory interconnect.
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A system comprising:
- a multicore processor including a plurality of cores and a memory controller to control communication between the multicore processor and a system memory of a first memory protocol, the memory controller to send mirrored command and address signals to the system memory via input/output (TO) connections of the multicore processor allocated to memory signals of a second memory protocol along a first point-to-point (PtP) interconnect and a second PtP interconnect;
- and
- the system memory coupled to the multicore processor and including a first memory device to receive the mirrored command and address signals via the first PtP interconnect and a second memory device to receive the mirrored command and address signals via the second PtP interconnect.
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Dependencies are inferred from the claim text.