US 2014/0006721 A1Published application

Information processing apparatus and cache controlling method

AssigneeFujitsu Limited

InventorsYuuji KONNO, Yasuhiro Kuroda

Life of this patent

Estimating the term…

Loading patent…

Abstract

When an uncorrectable error (UE) occurs in data read out from a second tag memory corresponding to a first tag memory of an arithmetic processing unit, a system controller issues a notification of WAY information of the second tag memory in which the UE has occurred to the arithmetic processing unit. The arithmetic processing unit degenerates a WAY of the corresponding first tag memory based on the received WAY information and issues a notification of completion of the degeneration process to the system controller. The system controller degenerates the WAY of the second tag memory in which the UE has occurred and re-issues a request relating to the UE after a notification that the degeneration process of the first tag memory is completed is received from the arithmetic processing unit.

Claims20

Dependent claims

An information processing apparatus, comprising:

an arithmetic processing unit including a cache memory and a first tag memory;
and
a system controller that performs communication control between the arithmetic processing unit and a different processing apparatus;
wherein
the system controller includes:
a command controlling unit that retains a request received from the arithmetic processing unit and re-issues the request when the request is not processed in a requesting destination;
a second tag memory that retains replicated data of data stored in the first tag memory;
and
a request controlling unit that issues, when an uncorrectable error (UE) occurs in data read out from the second tag memory, a notification of WAY information of the second tag memory in which the UE has occurred to the arithmetic processing unit, wherein
the arithmetic processing unit degenerates, when the notification of the occurrence of the UE is received from the request controlling unit, a WAY of the first tag memory corresponding to the WAY of the second tag memory in which the UE has occurred and then issues a notification that a degeneration process of the WAY of the first tag memory is completed to the request controlling unit;
and
the request controlling unit degenerates, when the UE occurs, the WAY of the second tag memory in which the UE has occurred, and receives the notification that the degeneration process of the first tag memory is completed from the arithmetic processing unit and then issues an instruction for causing the command controlling unit to re-issue a request relating to the UE.

9 more elements

A cache controlling method for an information processing apparatus including an arithmetic processing unit including a cache memory and a first tag memory, and a system controller that performs communication control between the arithmetic processing unit and a different processing apparatus, the method comprising:

issuing, by the system controller, when an uncorrectable error (UE) occurs in data read out from a second tag memory that retains replicated data of data stored in the first tag memory, a notification of WAY information of the second tag memory in which the UE has occurred to the arithmetic processing unit;
degenerating, by the arithmetic processing unit, when the notification of the occurrence of the UE is received, a WAY of the first tag memory corresponding to the WAY of the second tag memory in which the UE has occurred and then is suing a notification that a degeneration process of the WAY of the first tag memory is completed to the system controller;
and
degenerating, by the system controller, the WAY of the second tag memory in which the UE has occurred and receiving a notification that the degeneration process of the first tag memory is completed, from the arithmetic processing unit, and then re-issuing a request relating to the UE.

1 more element

Dependencies are inferred from the claim text.