Directory cache control device, directory cache control circuit, and directory cache control method

A directory cache control circuit comprising:

• a cache unit that caches a directory indicating an information processing apparatus caching information that is stored in a memory;
• a detection unit that detects an error in the directory that has occurred in the cache unit;
• a holding unit that holds, in a case an error is detected by the detection unit in tag information, a predetermined lower address of a memory address of the memory where information associated with the directory where the error has been detected is stored;
• a determination unit that determines, in a case a read request for information stored in the memory is received, whether a lower address of a memory address that is a target of the read request and the lower address that is being held by the holding unit match each other or not;
• and
• a control unit that controls, in a case the lower address of the memory address that is the target of the read request and the lower address that is being held by the holding unit are determined by the determination unit not to match each other, coherency of the information that is a target of the read request, based on a directory of the information that is the target of the read request.

A directory cache control method to be performed by a directory cache control device including a cache device that caches a directory indicating an information processing apparatus caching information stored in a memory, the directory cache control method comprising:

• detecting an error in the directory that has occurred in the cache device;
• holding, in a case the error is an error in tag information, a predetermined lower address of a memory address of the memory where information associated with the directory where the error has been detected is stored;
• determining, in a case a read request for information stored in the memory is received from another computer, whether a lower address of a memory address that is a target of the read request and the lower address that is being held match each other or not;
• and
• controlling, in a case the lower address of the memory address that is the target of the read request and the lower address that is being held are determined not to match each other, coherency of the information that is a target of the read request, based on a directory of the information that is the target of the read request.