Sub-numa clustering
AssigneeIntel Corporation
InventorsRavindra P. Saraf, Rahul Pal, Ashok Jagannathan
Life of this patent
Estimating the term…
Abstract
Method and apparatus to efficiently store and cache data. Cores of a processor and cache slices co-located with the cores may be grouped into a cluster. A memory space may be partitioned into address regions. The cluster may be associated with an address region from the address regions. Each memory address of the address region may be mapped to one or more of the cache slices grouped into the cluster. A cache access from one or more of the cores grouped into the cluster may be biased to the address region based on the association of the cluster with the address region.
Claims32
A method comprising:
- grouping a plurality of cores of a processor and a plurality of cache slices co-located with the plurality of cores into a cluster;
- partitioning a memory space into a plurality of address regions;
- associating the cluster with an address region of the plurality of address regions, wherein each memory address of the address region is mapped to at least one of the plurality of cache slices grouped into the cluster;
- and
- biasing a cache access from one or more of the plurality of cores grouped into the cluster to the address region based on the associating the cluster with the address region.
An apparatus comprising:
- a processor to execute computer instructions, wherein a plurality of cores of the processor and a plurality of cache slices co-located with the plurality of cores are grouped into a cluster, and the processor is configured to:
- partition a memory space into a plurality of address regions,
- associate the cluster with an address region of the plurality of address regions, wherein each memory address of the address region is mapped to at least one of the plurality of cache slices grouped into the cluster, and
- bias a cache access from one or more of the plurality of cores grouped into the cluster to the address region based on the association of the cluster with the address region.
An apparatus comprising:
- a processor to execute computer instructions, wherein a plurality of cores of the processor and a plurality of cache slices co-located with the plurality of cores are grouped into a cluster;
- and
- a memory, wherein the memory is partitioned into a plurality of address regions, the cluster is associated with an address region of the plurality of address regions, each memory address of the address region is mapped to at least one of the plurality of cache slices grouped into the cluster, and a cache access from one or more of the plurality of cores grouped into the cluster is biased to the address region based on the association of the cluster with the address region.
A non-transitory machine-readable medium having stored thereon an instruction, which if performed by a machine causes the machine to perform a method comprising:
- grouping a plurality of cores of a processor and a plurality of cache slices co-located with the plurality of cores into a cluster;
- partitioning a memory space into a plurality of address regions;
- associating the cluster with an address region of the plurality of address regions, wherein each memory address of the address region is mapped to at least one of the plurality of cache slices grouped into the cluster;
- and
- biasing a cache access from one or more of the plurality of cores grouped into the cluster to the address region based on the associating the cluster with the address region.
Dependencies are inferred from the claim text.