Row hammer refresh command
AssigneeIntel Corporation
InventorsKuljit S. Bains, John B. Halbert, Christopher P. Mozak, Theodore Z. Schoenborn, Zvika Greenfield
Life of this patent
Estimating the term…
Abstract
A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.
Claims30
A memory subsystem comprising:
- hardware connectors to couple to a memory device having multiple rows of memory;
- a memory controller coupled to the hardware connectors, the memory controller to
- receive an indication via the hardware connectors that repeated access to a specific row of the memory device exceeds a threshold;
- identify an address of the specific row;
- and
- send a command to the memory device to perform a targeted refresh, the command to cause the memory device to perform a refresh targeted to a victim row physically adjacent to the identified row.
An electronic device comprising:
- a memory subsystem having
- a memory device to store data, the memory device including multiple rows of memory;
- and
- a memory controller coupled to the memory device, the memory controller to receive an indication from the memory device that repeated access to a specific row of the memory device exceeds a threshold, identify an address of the specific row, and send a command to the memory device to perform a targeted refresh, the command to cause the memory device to perform a refresh targeted to a victim row physically adjacent to the identified row;
- and
- a multicore processor coupled to the memory subsystem to access the memory subsystem during execution of the processor.
A method comprising:
- receiving an indication that repeated access to a specific row of memory in a memory device exceeds a threshold;
- identifying an address of the row of memory;
- and
- sending a command to the memory device to perform a targeted refresh, the command to cause the memory device to perform a refresh targeted to a row physically adjacent to the identified row.
Dependencies are inferred from the claim text.