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US 2014/0006701 A1Published application
Hardware and Operating System Support for Persistent Memory On A Memory Bus
AssigneeMicrosoft Corporation
InventorsJeremy P. Condit, Edmund B. Nightingale, Benjamin C. Lee, Engin Ipek, Christopher Frost, Douglas C. Burger
Life of this patent
Estimating the term…
Abstract
Implementations of a file system that is supported by a non-volatile memory that is directly connected to a memory bus, and placed side by side with a dynamic random access memory (DRAM), are described.
Claims21
1-20. (canceled)
A processor comprising:
- a control component that enforces ordering and atomicity of memory writes;
- a memory component to enforce timing restraints in addition to the ordering and atomicity enforced by the control component;
- a non-volatile memory that is addressable by the control component;
- and
- a dynamic random access memory (DRAM), which shares an address space with the non-volatile memory.
2 more elements
A circuit comprising:
- a first component to enforce ordering and atomicity of writes to a memory component, the memory component addressable by a first component and including a non-volatile memory which shares an address space with a dynamic random access memory (DRAM);
- and
- a second component coupled to the first component to enforce timing restraints on the writes in addition to the ordering and atomicity enforced by the first component.
A processor comprising:
- a persistent memory addressable by a control component to enforce ordering of writes;
- and
- a dynamic random access memory (DRAM), which shares an address space with the persistent memory.
Dependencies are inferred from the claim text.