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US 2014/0006700 A1Published application
Configuration for power reduction in dram
AssigneeIntel Corporation
InventorsAndre Schaefer, John B. Halbert
Life of this patent
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Abstract
Disclosed embodiments may include an apparatus having a segment wordline enable coupled to logic to selectively disable ones of a number of segment wordline drivers. The logic may partition a page of the apparatus to reduce power consumed through activation of the disabled ones of the number of segment wordlines. Other embodiments may be disclosed.
Claims20
An apparatus, comprising:
- a plurality of segment wordline drivers configured to drive a plurality of segment wordlines, wherein each of the plurality of segment wordlines is coupled to a sub-array of memory cells;
- a master wordline coupled to plurality of segment wordline drivers, wherein the master wordline is responsive to row address strobe (RAS) signals received by the apparatus;
- a segment wordline enable coupled to logic to selectively disable ones of the plurality of segment wordline drivers to partition a page of the apparatus to reduce power consumed by activation of the disabled ones of the plurality of segment wordlines.
A dynamic random access memory (DRAM) stack, comprising:
- a first DRAM die including:
- a first plurality of segment wordline drivers each coupled to a first set of sub-arrays of memory cells and each configured to be responsive to a first master wordline signal;
- and
- a first segment wordline enable configured to selectively disable at least half of the first plurality of segment wordline drivers during operation to reduce total wordline power consumption of by the first DRAM die;
- and
- a second DRAM die coupled to the first in a stacked configuration and configured to transfer data to and from a memory controller in response to control signals received from the memory controller.
3 more elements
A method, comprising:
- receiving a master wordline signal, with a dynamic random access memory (DRAM), to drive a plurality of segment wordline drivers;
- receiving a segment wordline enable signal, with the DRAM, to selectively disable at least half of the segment wordline drivers from responding to the master wordline signal to partition a page of the DRAM to reduce power consumption by segment wordlines coupled to the disabled ones of the segment wordline drivers;
- and
- in response to a change of the segment wordline enable signal, selectively enabling some of the previously selectively disabled at least half of the segment wordline drivers.
1 more element
A system, comprising:
- a printed circuit board (PCB);
- a network interface coupled to the printed circuit board to transfer data to and from a network;
- and
- a processor having a dynamic random access memory (DRAM) stack configured as processor cache, the DRAM stack including:
- a first DRAM die including:
- a first plurality of segment wordline drivers each coupled to a first set of sub-arrays of memory cells and each configured to be responsive to a first master wordline signal;
- and
- a first segment wordline enable configured to selectively disable at least half of the first plurality of segment wordline drivers during operation to reduce total wordline power consumption of by the first DRAM die;
- and
- a second DRAM die coupled to the first in a stacked configuration and configured to transfer data to and from a memory controller in response to control signals received from the memory controller.
7 more elements
Dependencies are inferred from the claim text.