Flexible command addressing for memory
AssigneeIntel Corporation
InventorsKuljit S. Bains, John B. Halbert
Life of this patent
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Abstract
Flexible command addressing for memory. An embodiment of a memory device includes a dynamic random-access memory (DRAM); and a system element coupled with the DRAM, the system element including a memory controller for control of the DRAM. The DRAM includes a memory bank, a bus, the bus including a plurality of pins for the receipt of commands, and a logic, wherein the logic provides for shared operation of the bus for a first type of command and a second type of command received on a first set of pins.
Claims22
A memory device comprising:
- a dynamic random-access memory (DRAM);
- and
- a system element coupled with the DRAM, the system element including a memory controller for control of the DRAM;
- wherein the DRAM includes:
- a memory bank,
- a bus, the bus including a plurality of pins for the receipt of commands, and
- a logic, wherein the logic provides for shared operation of the bus for a first type of command and a second type of command received on a first set of pins.
A method comprising:
- initializing a dynamic random-access memory (DRAM);
- receiving a command for the DRAM, a command bus for the DRAM providing for shared operation for a first type of command and a second type of command, the bus having a first set of pins for the receipt of commands;
- interpreting the command, wherein interpreting the command includes:
- upon determining that a set of bits of the command are in a first state, interpreting the command as the first type of command, and
- upon determining that the set of bits of the command are in a second state, interpreting the command as the second type of command.
A system comprising:
- a processor to process data for the system;
- a transmitter, receiver, or both coupled with an omnidirectional antenna to transmit data, receive data, or both;
- and
- a memory device for the storage of data, the memory device including:
- a dynamic random-access memory (DRAM);
- and
- a system element coupled with the DRAM, the system element including a memory controller for control of the DRAM;
- wherein the DRAM includes:
- a memory bank,
- a bus, the bus including a plurality of pins for the receipt of commands, and
- a logic, wherein the logic provides for shared operation of the bus for column commands and row commands received on a first set of pins.
A non-transitory computer-readable storage medium having stored thereon data representing sequences of instructions that, when executed by a processor, cause the processor to perform operations comprising:
- initializing a dynamic random-access memory (DRAM);
- receiving a command for a command bus for the DRAM, the command bus providing for shared operation for column commands and row commands, the bus having a first set of pins for the receipt of commands;
- interpreting the command, wherein interpreting the command includes:
- upon determining that a set of bits of the command are in a first state, interpreting the command as a row command, and
- upon determining that the set of bits of the command are in a second state, interpreting the command as a column command.
Dependencies are inferred from the claim text.