Hybrid Cache State And Filter Tracking Of Memory Operations During A Transaction
AssigneeIntel Corporation
InventorsRobert S. Chappell, Ravi Rajwar, Zhongying Zhang, Jason A. Bessette
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AssigneeIntel Corporation
InventorsRobert S. Chappell, Ravi Rajwar, Zhongying Zhang, Jason A. Bessette
Estimating the term…
In one embodiment, a cache memory can store a plurality of cache lines, each including a write-set field to store a write-set indicator to indicate whether data has been speculatively written during a transaction of a transactional memory, and a read-set field to store a plurality of read-set indicators each to indicate whether a corresponding thread has read the data before the transaction has committed. A compression filter associated with the cache memory includes a first filter storage to store a representation of a cache line address of a cache line read by a first thread of threads before the transaction has committed. Other embodiments are described and claimed.
A processor comprising:
A method comprising:
A system comprising:
Dependencies are inferred from the claim text.