Endurance and Retention Flash Controller with Programmable Binary-Levels-Per-Cell Bits Identifying Pages or Blocks as having Triple, Multi, or Single-Level Flash-Memory Cells

A mixed-mode flash memory chip comprising:

• a flash memory having a plurality of flash memory cells that are Triple-Level-Cell (TLC) cells that are capable of storing three binary bits per physical flash memory cell, each flash memory cell having eight logic states determined by multiple voltage levels;
• wherein a block of the flash memory cells are capable of programming only one binary bit per physical memory cell when operating in a Single-Level-Cell (SLC) mode and are capable of programming two binary bits per physical memory cell when operating in a Multi-Level-Cell (MLC) mode;
• a plurality of voltage references generated from a first reference voltage, the plurality of voltage references being in a sequence of differing values;
• a plurality of comparators that generate a plurality of compare results by comparing a bit line connected to a flash memory cell to the plurality of voltage references;
• translation logic that receives the a plurality of compare results as inputs, and generates read data bits for the selected cell, wherein one read data bit is generated when operating in SLC mode, two read data bits are generated when operating in MLC mode, and wherein three read data bits are generated per flash memory cell when operating in TLC mode;
• and
• level bits that indicate when a strong page, a middle page, or a weak page is being programmed, wherein when only the strong page is programmed, reading is performed in the SLC mode, wherein when only the strong page and the middle page is programmed, reading is performed in the MLC mode, otherwise reading is performed in the TLC mode;
• wherein the level bits are applied to the translation logic, the level bits adjusting truth table logic within the translation logic to generate one read data bit for the SLC mode, to generate two read data bits for the MLC mode, and to generate three read data bits for the TLC mode, the truth table logic receiving the plurality of compare results as inputs and generating the read data bits as outputs that are a function of the plurality of compare results.

A retention Solid-State Drive (SSD) system comprising:

• a flash memory having a plurality of flash memory chips arranged into a plurality of channels, wherein the plurality of flash memory chips are Retention Multi-Level-Cell (RT-MLC) chips that are capable of storing two binary bits per physical flash memory cell, each flash memory cell having four logic states determined by multiple voltage levels;
• wherein the plurality of flash memory chips are capable of programming only one binary bit per physical memory cell when operating in a Single-Level-Cell (SLC) mode;
• a retention controller for controlling the plurality of flash memory chips, the retention controller comprising:
• a host interface for receiving host data;
• a dynamic-random-access memory (DRAM) buffer for storing a host Endurance Translation Layer (ETL);
• a flash interface for accessing the plurality of flash memory chips;
• wherein a programming voltage level or a programming pulse width is increased to increase retention of data within the flash memory cells;
• and
• a table manager for initializing, accessing, and managing tables in the DRAM buffer that are backed up to the flash memory, the tables including page status tables and bad block/erase count tables for blocks in the flash memory;
• wherein assigned-level bits are stored by the table manager for each block of the flash memory, the assigned-level bits indicating when a block of the flash memory operates in the SLC mode when accessing block data associated with a table entry, and when the block of flash memory operates in a MLC mode wherein two binary bits are stored per flash memory cell when accessing data associated with the table entry.

An endurance Solid-State Drive (SSD) system comprising:

• a flash memory having a plurality of flash memory chips arranged into a plurality of channels, wherein the plurality of flash memory chips are enterprise Multi-Level-Cell (eMLC) chips that are capable of storing two binary bits per physical flash memory cell, each flash memory cell having four logic states determined by multiple voltage levels;
• wherein the plurality of flash memory chips are capable of programming only one binary bit per physical memory cell when operating in a Single-Level-Cell (SLC) mode;
• an endurance controller for controlling the plurality of flash memory chips, the endurance controller comprising:
• a host interface for receiving host data;
• a dynamic-random-access memory (DRAM) buffer for storing a host Endurance Translation Layer;
• a flash interface for accessing the plurality of flash memory chips;
• wherein a programming voltage level or a programming pulse width is decreased to increase endurance of the flash memory cells;
• and
• a table manager for initializing, accessing, and managing tables in the DRAM buffer that are backed up to the flash memory, the tables including page status tables and bad block/erase count tables for blocks in the flash memory;
• wherein assigned-level bits are stored by the table manager for each block of the flash memory, the assigned-level bits indicating when a block of the flash memory operates in the SLC mode when accessing block data associated with a table entry, and when the block of the flash memory operates in a MLC mode wherein two binary bits are stored per flash memory cell when accessing data associated with the table entry.

A mixed-mode flash memory chip comprising:

• a flash memory having a plurality of flash memory cells that are Triple-Level-Cell (TLC) cells that are capable of storing three binary bits per physical flash memory cell, each flash memory cell having eight logic states determined by multiple voltage levels;
• wherein a block of the flash memory cells are capable of programming only one binary bit per physical memory cell when operating in a Single-Level-Cell (SLC) mode and are capable of programming two binary bits per physical memory cell when operating in a Multi-Level-Cell (MLC) mode;
• a plurality of voltage references generated from a first reference voltage, the plurality of voltage references being in a sequence of differing values;
• a plurality of comparators that generate a plurality of compare results by comparing a bit line connected to a flash memory cell to the plurality of voltage references;
• translation logic that receives the a plurality of compare results as inputs, and generates read data bits for the selected cell, wherein one read data bit is generated when operating in SLC mode, two read data bits are generated when operating in MLC mode, and wherein three read data bits are generated per flash memory cell when operating in TLC mode;
• and
• a level register for storing the level indicators programmed by firmware wherein it will determine the whole chip to be operated in SLC mode, MLC mode, or TLC mode or two external pins for determine the whole chip to be operated in SLC mode, MLC mode, or TLC mode.

A retention Solid-State Drive (SSD) system comprising:

• a flash memory having a plurality of flash memory chips arranged into a plurality of channels, wherein the plurality of flash memory chips are Retention Multi-Level-Cell (RT-MLC) chips that are capable of storing two binary bits per physical flash memory cell, each flash memory cell having four logic states determined by multiple voltage levels;
• wherein the plurality of flash memory chips are capable of programming only one binary bit per physical memory cell when operating in a Single-Level-Cell (SLC) mode;
• a retention controller for controlling the plurality of flash memory chips, the retention controller comprising:
• a host interface for receiving host data;
• a dynamic-random-access memory (DRAM) buffer for storing a host Endurance Translation Layer (ETL);
• a flash interface for accessing the plurality of flash memory chips;
• wherein an ETL firmware write to retention registers to increasing programming voltage level or increasing programming pulse width that increase retention of data within the flash memory cells;
• and
• an ETL firmware write to level register for storing the level indicators programmed by firmware wherein it will determine the whole chip to be operated in SLC mode, MLC mode, or by two hardwired external pins for determine the whole chip to be operated in SLC mode, or MLC mode;
• a backup power supply to power supply for powering the DRAM buffer storing the ETL and the flash memory.

An endurance Solid-State Drive (SSD) system comprising:

• a flash memory having a plurality of flash memory chips arranged into a plurality of channels, wherein the plurality of flash memory chips are Multi-Level-Cell (MLC) chips that are capable of storing two binary bits per physical flash memory cell, each flash memory cell having four logic states determined by multiple voltage levels;
• wherein the plurality of flash memory chips are capable of programming only one binary bit per physical memory cell when operating in a Single-Level-Cell (SLC) mode;
• a controller for controlling the plurality of flash memory chips, the endurance controller comprising:
• a host interface for receiving host data;
• a dynamic-random-access memory (DRAM) buffer for storing a host Endurance Translation Layer (ETL);
• a flash interface for accessing the plurality of flash memory chips;
• wherein an ETL firmware write to retention registers to decreasing programming voltage level or decreasing programming pulse width that increase endurance of data within the flash memory cells;
• an ETL firmware write to level register for storing the level indicators programmed by firmware wherein it will determine the whole chip to be operated in SLC mode, MLC mode or by two hardwired external pins for determine the whole chip to be operated in SLC mode, or MLC mode;
• and
• a backup power supply to a power supply for powering the DRAM buffer storing the ETL and the controller to refresh of flash memory.

An endurance Solid-State Drive (SSD) system comprising:

• a flash memory having a plurality of flash memory chips arranged into a plurality of channels, wherein the plurality of flash memory chips are Triple-Level-Cell (TLC) chips that are capable of storing three binary bits per physical flash memory cell, each flash memory cell having eight logic states determined by multiple voltage levels;
• wherein the plurality of flash memory chips are capable of programming only one binary bit per physical memory cell when operating in a Single-Level-Cell (SLC) mode, or programming only two binary bits per physical memory cell when operating in a Multi-Level-Cell (MLC) mode;
• an controller for controlling the plurality of flash memory chips, the endurance controller comprising:
• a host interface for receiving host data;
• a dynamic-random-access memory (DRAM) buffer for storing a host Endurance Translation Layer (ETL);
• a flash interface for accessing the plurality of flash memory chips;
• wherein an ETL firmware write to retention registers to decreasing programming voltage level or decreasing programming pulse width that increase endurance of data within the flash memory cells;
• and
• an ETL firmware write to level register for storing the level indicators programmed by firmware wherein it will determine the whole chip to be operated in SLC mode, MLC mode, TLC mode, or by two hardwired external pins for determine the whole chip to be operated in SLC mode, MLC mode, or TLC mode;
• a backup power supply to a power supply for powering the DRAM buffer and the controller to refresh the flash memory.

A retention Solid-State Drive (SSD) system comprising:

• a flash memory having a plurality of flash memory chips arranged into a plurality of channels, wherein the plurality of flash memory chips are Retention Triple-Level-Cell (RT-TLC) chips that are capable of storing three binary bits per physical flash memory cell, each flash memory cell having eight logic states determined by multiple voltage levels;
• wherein the plurality of flash memory chips are capable of programming only two binary bits per physical memory cell when operating in a Multi-Level-Cell (MLC) mode;
• wherein the plurality of flash memory chips are capable of programming only one binary bit per physical memory cell when operating in a Single-Level-Cell (SLC) mode;
• a retention controller for controlling the plurality of flash memory chips, the retention controller comprising:
• a host interface for receiving host data;
• a dynamic-random-access memory (DRAM) buffer for storing a host Endurance Translation Layer;
• a flash interface for accessing the plurality of flash memory chips;
• wherein a programming voltage level or a programming pulse width is increased to increase retention of data within the flash memory cells;
• and
• a table manager for initializing, accessing, and managing tables in the DRAM buffer that are backed up to the flash memory, the tables including page status tables and bad block/erase count tables for blocks in the flash memory;
• wherein assigned-level bits are stored by the table manager for each block of the flash memory, the assigned-level bits indicating when a block of the flash memory operates in the SLC mode when accessing block data associated with a table entry, and when the block of flash memory operates in the MLC mode wherein two binary bits are stored per flash memory cell when accessing data associated with the table entry, and when the block of flash memory operates in the TLC mode wherein three binary bits are stored per flash memory cell when accessing data associated with the table entry.