Memory management in a virtualization environment
AssigneeBroadcom Corporation
InventorsWei-Hsiang CHEN, Ricardo RAMIREZ, Hai N. NGUYEN
Life of this patent
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Abstract
An architecture is described for performing memory management in a virtualization environment. Multiple levels of caches are provided to perform address translations, where at least one of the caches contains a mapping between a guest virtual address and a host physical address. This type of caching implementation serves to minimize the need to perform costly multi-stage translations in a virtualization environment.
Claims52
A system for performing memory management, comprising:
- a first level cache, wherein the first level cache comprises a single lookup structure to translate between a guest virtual address and a host physical address, in which the guest virtual address corresponds to a guest virtual memory for software that operates within a virtual machine, the virtual machine corresponding to virtual physical memory is accessible using a guest physical address, and wherein the virtual machine corresponds to a host physical machine having host physical memory accessible by the host physical address;
- and
- a second level cache, wherein the second level cache comprises a multiple lookup structure to translate between the guest virtual address and the host physical address.
A method implemented with a processor for performing memory management, comprising:
- accessing a first level cache to perform a single lookup operation to translate between a guest virtual address and a host physical address;
- and
- accessing a second level cache if a cache miss occurs at the first level cache, wherein a first lookup operation is performed at the second level cache to translate between the guest virtual address and a guest physical address, and a second lookup operation is performed at the second level cache to translate between the guest physical address and the host physical address.
A memory management structure, comprising:
- a content addressable memory (CAM) comprising pointer entries to a first memory device and a second memory device;
- the first memory device comprising a first set of stored content;
- and
- the second memory device comprising a second set of stored content, wherein both the first memory device and the second memory device are parallel downstream devices referenceable by the CAM using a single input data value to access both the first set of stored. content and the second set of stored content,
A method, comprising:
- providing a single input to a content addressable memory (CAM);
- and
- searching the CAM using the single input to identify pointers to entries to a first memory device and a second memory device, wherein both the first memory device and the second memory device are parallel downstream devices that are referenceable by the CAM using the single input to access both a first set of stored content in the first memory device and a second set of stored content in the second memory device.
Dependencies are inferred from the claim text.