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US 2014/0006668 A1Published application
Performing Emulated Message Signaled Interrupt Handling
AssigneeIntel Corporation
InventorYen Hsiang Chew
Life of this patent
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Abstract
In an embodiment, a processor includes a logic to store a write transaction including an interrupt and data received from a device coupled to the processor to a cache line of a cache memory based on an address in an address queue, and forward an address of the cache line and assert an emulated message signaling interrupt (MSI) signal to an interrupt controller of the processor. Other embodiments are described and claimed.
Claims28
A processor comprising:
- a first logic to store a write transaction including an interrupt and data received from a device coupled to the processor to a cache line of a cache memory based on an address in an address queue, and forward an address of the cache line and assert an emulated message signaling interrupt (MSI) signal to an interrupt controller of the processor;
- the interrupt controller coupled to the first logic to obtain the data stored in the cache line responsive to the emulated MSI signal and to assign at least one interrupt vector of the data to a first core of the processor to cause the first core to handle the interrupt;
- and
- the first core coupled to the interrupt controller and including at least one execution unit to perform operations responsive to an interrupt handler accessed via the at least one interrupt vector.
1 more element
An apparatus comprising:
- a first core to execute instructions;
- a second core to execute instructions;
- a cache memory coupled to the first and second cores and including a plurality of cache lines, wherein a first portion of cache lines are to be locked for allocation to incoming write transactions from a plurality of devices coupled to the processor;
- and
- a decode logic to store a write transaction received from a first device of the plurality of devices to a cache line of the first portion of cache lines, and assert an emulated message signaling interrupt (MSI) signal;
- an interrupt controller to obtain data stored in the cache line responsive to the emulated MSI signal and to assign at least one interrupt vector of the write transaction to the first core.
3 more elements
A system comprising:
- a first processor including a plurality of first cores and an interrupt controller coupled to a first cache memory to store a cache line including a plurality of interrupt vectors each associated with interrupt data, to remove a first portion of the interrupt vectors and the associated interrupt data for a first plurality of interrupts to be handled within the plurality of first cores to form a modified cache line data, and to forward the modified cache line data as an inter-processor interrupt to a second processor coupled to the processor;
- the second processor coupled to the first processor and including at least one second core, a second cache memory to receive and store the modified cache line data, and a second interrupt controller to access the modified cache line data and to obtain at least one interrupt vector and corresponding data for an interrupt to be handled by the at least one second core;
- and
- a dynamic random access memory (DRAM) coupled to the first and second processors.
1 more element
Dependencies are inferred from the claim text.