US 2014/0006659 A1Published application

Driver-assisted base address register mapping

AssigneeIntel Corporation

InventorsAnnie Foong, Pak-Lung Seto

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Abstract

Techniques herein include systems and methods for driver-assisted BAR mapping that virtualize PCI functions, but without virtualizing the storage media itself. Such techniques make use of unused BARs (Base Address Registers) of a master (Operating system-facing) device to gain access to other PCIe logical instances, while still exposing only a single PCIe function (connection or channel) to system software. This technique provides a new concept of logical PCIe device instances through BAR mapping by making use of unused BARs to extend access to any number of PCIe instances or memory-mapped I/O devices behind a master device such that only a single PCIe function is exposed to system software. Embodiments can thus extend access to one or more additional storage devices through one level of BAR indirection. As a result, such techniques and embodiments enable the multiplication of storage capacity and performance through the aggregation of multiple, similar hardware components.

Claims20

Dependent claims

A data storage device comprising:

a storage aggregation unit that has multiple memory-mapped input/output (I/O) devices interconnected within the storage aggregation unit, each memory-mapped I/O device has multiple Base Address Registers, the storage aggregation unit includes a physical connection interface configured to connect to a computer bus;
the storage aggregation unit including a processor and a memory coupled to the processor, the memory storing instructions that, when executed by the processor, causes the storage aggregation unit to perform the operations of:
receiving a memory access request at a first memory-mapped I/O device of the storage aggregation unit;
in response to the memory access request identifying a physical address within a first Base Address Register of the first memory-mapped I/O device, executing the memory access request on the first memory-mapped I/O device;
and
in response to the memory access request identifying a physical address within a second Base Address Register of the first memory-mapped I/O device, redirecting the memory access request to a second memory-mapped I/O device, of the multiple interconnected memory-mapped I/O devices, and executing the memory access request on the second memory-mapped I/O device.

3 more elements

A method comprising:

receiving a memory access request at a first memory-mapped I/O device of a storage aggregation unit, the storage aggregation unit including multiple interconnected memory-mapped I/O devices, each memory-mapped I/O device having multiple Base Address Registers;
in response to the memory access request identifying a physical address within a first Base Address Register of the first memory-mapped I/O device, executing the memory access request on the first memory-mapped I/O device;
and
in response to the memory access request identifying a physical address within a second Base Address Register of the first memory-mapped I/O device, redirecting the memory access request to a second memory-mapped I/O device, of the multiple interconnected memory-mapped I/O devices, and executing the memory access request on the second memory-mapped I/O device.

1 more element

A computer program product including a non-transitory computer-storage medium having instructions stored thereon for processing data information, such that the instructions, when carried out by a processing device, cause the processing device to perform the operations of:

receiving a memory access request at a first memory-mapped I/O device of a storage aggregation unit, the storage aggregation unit including multiple interconnected memory-mapped I/O devices, each memory-mapped I/O device having multiple Base Address Registers;
in response to the memory access request identifying a physical address within a first Base Address Register of the first memory-mapped I/O device, executing the memory access request on the first memory-mapped I/O device;
and
in response to the memory access request identifying a physical address within a second Base Address Register of the first memory-mapped I/O device, redirecting the memory access request to a second memory-mapped I/O device, of the multiple interconnected memory-mapped I/O devices, and executing the memory access request on the second memory-mapped I/O device.

1 more element

Dependencies are inferred from the claim text.