Semiconductor memory device and method of operating the semiconductor memory device

A method of controlling an order of executing commands of a plurality of master groups including a first master group and a second master group in a semiconductor system including a memory controller, comprising:

• generating a first timeout index signal, by a first master in the first master group, based on a residual memory capacity of a first data buffer in the first master;
• generating a second timeout index signal, by a second master in the second master group, based on a residual memory capacity of a second data buffer in the second master;
• comparing the residual memory capacity of the first data buffer with a first threshold value of the residual memory capacity of the first data buffer;
• comparing the residual memory capacity of the second data buffer with a second threshold value of the residual memory capacity of the second data buffer;
• if the residual memory capacity of the first data buffer in the first master is larger than the first threshold value of the residual memory capacity of the first data buffer, selecting, among a first timeout value and a second timeout value, by the memory controller, the second timeout value for the first master in response to the first timeout index signal, the second timeout value being larger than the first timeout value, and if the residual memory capacity of the first data buffer in the first master is less than the first threshold value of the residual memory capacity of the first data buffer, selecting the first timeout value for the first master in response to the first timeout index signal;
• if the residual memory capacity of the second data buffer in the second master is larger than the second threshold value of the residual memory capacity of the second data buffer, selecting, among a third timeout value and a fourth timeout value, by the memory controller, the fourth timeout value for the second master, in response to the second timeout index signal, the fourth timeout value being larger than the third timeout value, and if the residual memory capacity of the second data buffer in the second master is less than the second threshold value of the residual memory capacity of the second data buffer, selecting the third timeout value for the second master in response to the second timeout index signal;
• and
• determining, by the memory controller, the order of executing the commands based on the selected timeout value for the first master and the selected timeout value for the second master.

A method of controlling an order of executing commands of a plurality of master groups including a first master group and a second master group in a semiconductor system including a memory controller, comprising:

• generating a first timeout index signal, by a first master in the first master group, based on a residual memory capacity of a first data buffer in the first master;
• generating a second timeout index signal, by a second master in the second master group, based on a residual memory capacity of a second data buffer in the second master;
• selecting a first timeout value, by the memory controller, among a plurality of timeout values associated with the first master group in response to the first timeout index signal;
• selecting a second timeout value, by the memory controller, among a plurality of timeout values associated with the second master group in response to the second timeout index signal;
• counting, by the memory controller, the selected timeout values including the first timeout value and the second timeout value, the counting the selected timeout values including incrementing or decrementing, by the memory controller, the selected timeout values until at least one of the selected timeout values reaches to a predetermined value;
• giving a priority to a first command from the first master if the first timeout value reaches to the predetermined value before the second timeout value reaches to the predetermined value, or giving a priority to a second command from the second master if the second timeout value reaches to the predetermined value before the first timeout value reaches to the predetermined value;
• and
• determining, by the memory controller, the order of executing the commands based on a result of the giving the priority.

A method of controlling an order of executing commands of a plurality of masters including a first master and a second master in a semiconductor system including a memory controller, comprising:

• generating a first timeout index signal, by the first master, based on a residual memory capacity of a first data buffer in the first master;
• generating a predetermined second timeout index signal, by the second master;
• among a first timeout value and a second timeout value associated with the first master, the second timeout value being larger than the first timeout value, selecting either the first timeout value or the second timeout value for the first master, by the memory controller, in response to the first timeout index signal;
• generating a predetermined second timeout value for the second master, by the memory controller, in response to the second timeout index signal, the predetermined second timeout value being larger than the first timeout value and being less than the second timeout value;
• and
• determining, by the memory controller, the order of executing the commands based on the selected timeout values.

A method of controlling an order of executing commands of a plurality of masters including a first master and a second master in a semiconductor system including a memory controller, comprising:

• generating a first timeout index signal, by the first master, based on a residual memory capacity of a first data buffer in the first master;
• transmitting the first timeout index signal from the first master to the memory controller either via a data bus or via a first route between the first master and the memory controller, the first route being separate and independent of the data bus;
• generating a second timeout index signal, by the second master, based on a residual memory capacity of a second data buffer in the second master;
• transmitting the second timeout index signal from the second master to the memory controller either via the data bus or via a second route between the second master and the memory controller, the second route being separate and independent of the data bus;
• and
• determining the order of executing the commands based on timeout index signals including the first and the second timeout index signals.

A memory controller for controlling an order of executing commands of a plurality of master groups, each of the plurality of master group including at least one master, comprising:

• a register block configured to select a timeout value for each master among a plurality of timeout values associated with that master in response to a timeout index signal from that master;
• a queue configured to determine the order of executing the commands based on the selected timeout values;
• a timeout counter configured to count the selected timeout values and output a result to the queue;
• and
• a synchronous logic circuit configured to synchronize an operating frequency of each master with a driving frequency of a semiconductor memory device,
• wherein the register block includes a plurality of registers that contain a group identification indicating which master group a particular master belongs to, a group mask identifying the particular master in the master group, and at least one timeout values of the particular master.

A semiconductor system comprising:

• a plurality of master groups including a first master group and a second master group, the first master group including a first master, the second master group including a second master;
• a memory controller;
• a data bus connecting the memory controller and the first master and connecting the memory controller and the second master;
• a first channel connecting the first master and the memory controller, the first channel being separate and independent of the data bus;
• and
• a second channel connecting the second master and the memory controller, the second channel being separate and independent of the data bus,
• wherein the first master is configured to generate a first timeout index signal based on a residual memory capacity of a first data buffer in the first master and transmit the first timeout index signal either via the data bus or via the first channel,
• the second master is configured to generate a second timeout index signal based on a residual memory capacity of a second data buffer in the second master and transmit the second timeout index signal either via the data bus or via the second channel, and
• the memory controller is configured to set at least one timeout value for the first master group among a plurality of timeout values associated with the first master group in response to the first timeout index signal, set at least one timeout value for the second master group among a plurality of timeout values associated with the second master group in response to the second timeout index signal, and determine an order of executing commands based on the timeout values.

A method of controlling an order of executing commands of a plurality of masters including a first master and a second master in a semiconductor system including a memory controller, comprising:

• generating a first timeout index signal, by the first master, based on a residual memory capacity of a first data buffer in the first master;
• generating a second timeout index signal, by the second master, based on a residual memory capacity of a second data buffer in the second master;
• selecting one timeout value for the first master, by the memory controller, in response to the first timeout index signal;
• selecting one timeout value for the second master, by the memory controller, in response to the second timeout index signal;
• and
• determining, by the memory controller, the order of executing the commands based on the selected timeout values.

A method of controlling an order of executing commands of a plurality of masters including a first master and a second master in a semiconductor system including a memory controller, comprising:

• generating a first timeout index signal, by the first master, based on a residual memory capacity of a first data buffer in the first master;
• generating a predetermined second timeout index signal, by the second master;
• among a first timeout value and a second timeout value associated with the first master, the second timeout value being larger than the first timeout value, selecting either the first timeout value or the second timeout value for the first master, by the memory controller, in response to the first timeout index signal;
• among a third timeout value and a fourth timeout value associated with the second master, the fourth timeout value being larger than the third timeout value, selecting either the third timeout value or the fourth timeout value for the second master, by the memory controller, in response to the second timeout index signal;
• and
• determining, by the memory controller, the order of executing the commands based on the selected timeout values.