Semiconductor Device Using Serial ATA Protocol and System Including the Same
AssigneeSamsung Electronics Co., Ltd.
InventorsYoung-Jin Cho, Ho-Ha Kim
Life of this patent
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Abstract
A semiconductor device includes a delay unit determining a delay value. A FIS (Frame Information Structure) receiver is connected to a transfer channel and receives a first H2D (Host to Device) FIS including first command information. A FIS generator is connected to a receiving channel and successively outputs a first DMA (Direct Memory Access) setup FIS, a first data FIS, and a first SDB (Set Device Bits) FIS after outputting a first D2H (Device to Host) FIS in response to the first H2D FIS, and to insert a delay period as large as the delay value next to the first data FIS or the first SDB FIS.
Claims20
A semiconductor device comprising:
- a delay unit determining a delay value;
- a Frame Information Structure (FIS) receiver connected to a transfer channel and receiving a first Host to Device (H2D) FIS including first command information;
- and
- a FIS generator connected to a receiving channel and successively outputting a first Direct Memory Access {DMA) setup FIS, a first data FIS, and a first Set Device Bits (SDB) FIS after outputting a first Device to Host (D2H) FIS in response to the first H2D FIS, and inserting a delay period, having the delay value, next to either the first data FIS or the first SDB FIS.
A semiconductor device comprising:
- a Frame Information Structure (FIS) receiver successively receiving first to n-th (where, n is a natural number that is equal to or larger than 2) Host to Device (H2D) FIS that include first to n-th command information, respectively;
- and
- a FIS generator successively outputting first to m-th (where, m is a natural number that is equal to or larger than 2) FIS related to the first to n-th command information after successively outputting first to n-th D2H FIS in response to the first to n-th H2D FIS,
- wherein while the FIS generator outputs only parts of the first to m-th FIS, the FIS receiver receives the (n+1)-th H2D FIS, and
- the FIS generator outputs the (n+1)-th D2H FIS in response the (n+1)-th H2D FIS, between a k-th (where, k is a natural number that satisfies 1<k<m) FIS and a (k+1)-th FIS.
A method for conducting Serial Advanced Technology Attachment (SATA) communication, comprising:
- determining a delay value;
- receiving a first Host to Device (H2D) Frame Information Structure (FIS) including first command information;
- and
- successively outputting a first Direct Memory Access (DMA) setup FIS, a first data FIS, and a first Set Device Bits (SDB) FIS after outputting a first Device to Host (D2H) FIS in response to the first H2D FIS, and inserting a delay period, having the delay value, next to either the first data FIS or the first SDB FIS.
Dependencies are inferred from the claim text.