Address Remapping Using Interconnect Routing Identification Bits

An electronic system, comprising:

• a plurality of processors;
• at least one common memory;
• a bus interconnect coupled with the plurality of processors and the at least one common memory, the bus interconnect being operative to receive a first address corresponding to a bus transaction between a given one of the plurality of processors and the common memory and to decode a unique identifier associated with the given one of the plurality of processors;
• and
• a remapping module coupled with an output of the bus interconnect, the remapping module being operative to generate a second address as a function of the first address and the unique identifier for remapping access to the common memory by the given one of the plurality of processors.

An apparatus for facilitating address mapping between one or more master devices and at least one common slave device in a multiprocessor system, the apparatus comprising:

• at least one processor in operative communication with the one or more master devices and the at least one slave device, the at least one processor being operative:
• (i) to receive a first address corresponding to a bus transaction between a given one of the one or more master devices and the at least one slave device;
• (ii) to decode a unique identifier associated with the given one of the one or more master devices;
• and (iii) to generate a second address as a function of the first address and the unique identifier for remapping access to the at least one slave device by the given one of the one or more master devices.