Test bench transaction synchronization in a debugging environment

A method comprising:

• parsing, by a computing system, a simulation log corresponding to operation of a test bench during a simulation of a circuit design to extract test bench transactions from the simulation log;
• and
• synchronizing, by the computing system, the test bench transactions from the simulation log with waveform data generated during the simulation of the circuit design;
• and
• prompting, by the computing system, display of the test bench transactions and the simulated output for the circuit design in temporal synchronization with each other.

An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:

• parsing a simulation log corresponding to operation of a test bench during a simulation of a circuit design to extract test bench transactions from the simulation log;
• and
• synchronizing the test bench transactions from the simulation log with waveform data generated during the simulation of the circuit design;
• and
• prompting display of the test bench transactions and the simulated output for the circuit design in temporal synchronization with each other.

An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:

• simulating a circuit design with a test bench to generate a simulated output for the circuit design and a simulation log corresponding to operation of the test bench during the simulation of the circuit design;
• determining whether the simulated output for the circuit design is different than an expected output for the circuit design;
• and
• synchronizing the simulated output for the circuit design with test bench transactions from the simulation log that prompted the generation of the simulated output for the circuit design when the simulated output of the circuit design is different than the expected output of the circuit design.