Time-variant antenna enabled by switched capacitor array on silicon
AssigneeIntel Corporation
InventorsSEONG-YOUP SUH, Ricardo Suarez-Gartner
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Abstract
A time-variant antenna is disclosed that uses a switched capacitor array in silicon to improve the performance and integration options of the time-variant antenna. Parasitic effects of the interface between the on-board antenna and on-silicon switched capacitor array are considered and the antenna is tuned to compensate for these effects. The switched capacitor array provides high linearity, lower cost, and reduced size, relative to prior art antenna implementations.
Claims27
A time-variant antenna system, comprising:
- an antenna coupled to a transceiver, the antenna being disposed upon an antenna board, wherein the antenna comprises a frequency response;
- and
- a switched capacitor logic coupled to the antenna through an interface, wherein the switched capacitor logic is disposed upon a silicon surface, the switched capacitor logic further comprising:
- a plurality of capacitors;
- a plurality of switches, wherein each switch is coupled between a ground and its respective capacitor of the plurality of capacitors;
- and
- a control logic to enable or disable a switch of the plurality of switches;
- wherein the switched capacitor logic controls the frequency response of the antenna.
A switched capacitor logic unit disposed on a silicon substrate, the switched capacitor logic unit comprising:
- a plurality of capacitors arranged in a parallel array;
- a plurality of switches, wherein each switch is coupled between a ground and its respective capacitor in the parallel array;
- and
- a control logic to enable or disable one or more switches of the plurality of switches;
- wherein the switched capacitor logic tunes a frequency range of an antenna disposed on an antenna board while considering a parasitic effect of an interface between the parallel array and the antenna.
A processor-based system disposed on a system board, the processor-based system comprising:
- a central processing unit (CPU);
- a memory coupled to the CPU;
- an antenna coupled to a transceiver;
- and
- a switched capacitor logic unit, the switched capacitor logic unit comprising:
- a plurality of capacitors arranged in a parallel array;
- a plurality of switches, wherein each switch is coupled between a ground and its respective capacitor in the parallel array;
- and
- a control logic to enable or disable one or more switches of the plurality of switches, the control logic comprising a software program to be loaded into the memory and executed by the processor;
- wherein the switched capacitor logic tunes a frequency range of the antenna while considering a parasitic effect of an interface between the parallel array and the antenna.
Dependencies are inferred from the claim text.