Devices, systems, and methods related to planarizing semiconductor devices after forming openings

A method for forming through-substrate vias in a semiconductor device, comprising:

• forming openings through at least a portion of a substrate of the semiconductor device;
• forming a dielectric layer including a liner portion at sidewalls of the openings and excess dielectric material at areas outside the openings;
• forming a metal layer including via portions within the openings and excess metal;
• simultaneously chemically-mechanically removing the excess metal and the excess dielectric material such that the via portions are electrically separated from one another at one end;
• and
• removing at least a portion of the substrate such that opposing ends of the via portions are exposed and the via portions form through-substrate vias.

A method for forming vias in a semiconductor device, comprising:

• forming openings through at least a portion of a substrate of the semiconductor device;
• forming a dielectric layer of the semiconductor device, the dielectric layer including a liner portion on sidewalls of the openings and excess dielectric material outside the openings;
• forming a copper layer of the semiconductor device, the copper layer including copper vias within the openings and excess copper outside the openings;
• and
• simultaneously chemically-mechanically removing the excess copper and the excess dielectric material using a slurry including ceria.

A method of processing a semiconductor device including a first dielectric material, comprising:

• forming a second dielectric layer of the semiconductor device;
• forming a third dielectric layer of the semiconductor device, the second dielectric layer being generally between the third dielectric layer and a substrate of the semiconductor device;
• forming a barrier layer of the semiconductor device, the second and third dielectric layers being generally between the barrier layer and the substrate;
• forming a metal layer of the semiconductor device, the metal layer including plug portions within openings of the semiconductor device and excess metal;
• and
• chemically-mechanically processing the semiconductor device, including—
• simultaneously chemically-mechanically removing the excess metal and the barrier layer outside the openings until the barrier layer outside the openings is generally removed, and
• simultaneously chemically-mechanically removing the excess metal and the third dielectric layer outside the openings until the third dielectric layer outside the openings is generally removed.

A method, comprising:

• forming a stop layer of a semiconductor device;
• forming openings in the semiconductor device, wherein individual openings have a sidewall extending through the stop layer and through at least a portion of a substrate of the semiconductor device;
• forming a dielectric liner including a first portion along the sidewalls of the openings and a second portion at areas outside the openings, wherein the stop layer is generally between the dielectric liner and the substrate at the areas outside the openings;
• forming a barrier/seed structure of the semiconductor device, the stop layer and the dielectric liner being generally between the barrier/seed structure and the substrate at the areas outside the openings;
• electroplating copper onto the barrier/seed structure to form a copper layer including copper plugs within the openings and excess copper over the copper plugs and the second portion of the dielectric liner;
• and
• chemically-mechanically removing the second portion of the dielectric liner using a slurry including ceria to expose the stop layer after electroplating the copper.