Methods for fabricating integrated circuits having improved metal gate structures
AssigneeGlobalfoundries Inc.
InventorKim Hoon
Life of this patent
Estimating the term…
Loading patent…
AssigneeGlobalfoundries Inc.
InventorKim Hoon
Estimating the term…
Methods for fabricating integrated circuits are provided. One method includes forming first and second FET trenches in an interlayer dielectric material on a semiconductor substrate. The first FET trench is partially filled with a first work function metal to define an inner cavity in the first FET trench. The first work function metal is a N-type work function metal or a P-type work function metal. The N-type work function metal is selected from the group consisting of titanium, tantalum, hafnium, ytterbium silicide, erbium silicide, and titanium silicide. The P-type work function metal is selected from the group consisting of cobalt, nickel, and tungsten silicide. The inner cavity and the second FET trench are filled with a second work function metal to form corresponding metal gate structures. The second work function metal is the other of the N-type work function metal or the P-type work function metal.
A method for fabricating an integrated circuit, the method comprising:
A method for fabricating an integrated circuit, the method comprising:
A method for fabricating an integrated circuit, the method comprising:
Dependencies are inferred from the claim text.