Method of manufacturing semiconductor device
AssigneeKabushiki Kaisha Toshiba
InventorsTatsunori ISOGAI, Tomonori Aoyama
Life of this patent
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Abstract
In one embodiment, a method of manufacturing a semiconductor device includes forming a transistor including a gate insulator and a gate electrode on a substrate. The method further includes forming an interconnect structure including one or more interconnect layers on the substrate by performing first and second processes one or more times, the first process forming an interconnect layer on the substrate, and the second process processing the interconnect layer into an interconnect pattern. The method further includes annealing the substrate by irradiating the substrate with a microwave, after at least one interconnect layer included in the one or more interconnect layers is processed into an interconnect pattern on the substrate.
Claims20
A method of manufacturing a semiconductor device, the method comprising:
- forming a transistor including a gate insulator and a gate electrode on a substrate;
- forming an interconnect structure including one or more interconnect layers on the substrate by performing first and second processes one or more times, the first process forming an interconnect layer on the substrate, and the second process processing the interconnect layer into an interconnect pattern;
- and
- annealing the substrate by irradiating the substrate with a microwave, after at least one interconnect layer included in the one or more interconnect layers is processed into an interconnect pattern on the substrate.
A method of manufacturing a semiconductor device, the method comprising:
- forming a transistor for a logic circuit on a substrate, the transistor including a gate insulator and a gate electrode;
- forming an interconnect structure including one or more interconnect layers on the substrate by performing first and second processes one or more times, the first process forming an interconnect layer on the substrate, and the second process processing the interconnect layer into an interconnect pattern;
- and
- annealing the substrate by irradiating the substrate with a microwave, after a bottommost interconnect layer included in the one or more interconnect layers is formed on the substrate and the bottommost interconnect layer is processed into an interconnect pattern.
A method of manufacturing a semiconductor device, the method comprising:
- forming a transistor for a memory circuit on a substrate, the transistor including a gate insulator and a gate electrode;
- forming an interconnect structure including N interconnect layers on the substrate by performing first and second processes N times, where N is an integer of 2 or more, the first process forming an interconnect layer on the substrate, and the second process processing the interconnect layer into an interconnect pattern;
- and
- annealing the substrate by irradiating the substrate with a microwave, after a (K+1)-th interconnect layer is formed on the substrate and the (K+1)-th interconnect layer is processed into an interconnect pattern, in a case where the N interconnect layers include one or more interconnect layers including memory elements and a K-th interconnect layer is a topmost interconnect layer included in the one or more interconnect layers, where K is an integer satisfying a relation of 1≦K≦N−1.
Dependencies are inferred from the claim text.